ARM architecture

Arm (previously officially written all caps as ARM and usually written as such today), previously Advanced RISC Machine, originally Acorn RISC Machine, is a family of reduced instruction set computing (RISC) architectures for computer processors, configured for various environments. Arm Holdings develops the architecture and licenses it to other companies, who design their own products that implement one of those architectures‍—‌including systems-on-chips (SoC) and systems-on-modules (SoM) that incorporate memory, interfaces, radios, etc. It also designs cores that implement this instruction set and licenses these designs to a number of companies that incorporate those core designs into their own products.

For the Australian architectural firm, see ARM Architecture (Ashton Raggatt McDougall). For processor core designs, see List of ARM microarchitectures.

Arm architectures
The Arm logo
DesignerArm Holdings
Bits32-bit, 64-bit
Introduced1985 (1985)
DesignRISC
TypeRegister-Register
BranchingCondition code, compare and branch
OpenProprietary
64/32-bit architectures
Introduced2011 (2011)
VersionArmv8-A, Armv8.1-A, Armv8.2-A, Armv8.3-A, Armv8.4-A, Armv8.5-A, Armv8.6-A
EncodingAArch64/A64 and AArch32/A32 use 32-bit instructions, T32 (Thumb-2) uses mixed 16- and 32-bit instructions; ARMv7 user-space compatibility.[1]
EndiannessBi (little as default)
ExtensionsSVE;SVE2;TME; All mandatory: Thumb-2, NEON, VFPv4-D16, VFPv4 Obsolete: Jazelle
Registers
General purpose31 × 64-bit integer registers[1]
Floating point32 × 128-bit registers[1] for scalar 32- and 64-bit FP or SIMD FP or integer; or cryptography
32-bit architectures (Cortex)
VersionArmv8-R, Armv8-M, Armv8.1-M, Armv7-A, Armv7-R, Armv7E-M, Armv7-M, Armv6-M
Encoding32-bit, except Thumb-2 extensions use mixed 16- and 32-bit instructions.
EndiannessBi (little as default); Cortex-M is fixed and can't change on the fly.
ExtensionsThumb-2, Neon, Jazelle, DSP, Saturated, FPv4-SP, FPv5, Helium
Registers
General purpose15 × 32-bit integer registers, including R14 (link register), but not R15 (PC)
Floating pointUp to 32 × 64-bit registers,[2] SIMD/floating-point (optional)
32-bit architectures (legacy)
VersionARMv6, ARMv5, ARMv4T, ARMv3, ARMv2
Encoding32-bit, except Thumb extension uses mixed 16- and 32-bit instructions.
EndiannessBi (little as default) in ARMv3 and above
ExtensionsThumb, Jazelle
Registers
General purpose15 × 32-bit integer registers, including R14 (link register), but not R15 (PC, 26-bit addressing in older)

Processors that have a RISC architecture typically require fewer transistors than those with a complex instruction set computing (CISC) architecture (such as the x86 processors found in most personal computers), which improves cost, power consumption, and heat dissipation. These characteristics are desirable for light, portable, battery-powered devices‍—‌including smartphones, laptops and tablet computers, and other embedded systems[3][4][5]‍—‌but are also useful for servers and desktops to some degree. For supercomputers, which consume large amounts of electricity, Arm is also a power-efficient solution.[6]

Arm Holdings periodically releases updates to the architecture. Architecture versions Armv3 to Armv7 support 32-bit address space (pre-Armv3 chips, made before Arm Holdings was formed, as used in the Acorn Archimedes, had 26-bit address space) and 32-bit arithmetic; most architectures have 32-bit fixed-length instructions. The Thumb version supports a variable-length instruction set that provides both 32- and 16-bit instructions for improved code density. Some older cores can also provide hardware execution of Java bytecodes; and newer ones have one instruction for JavaScript. Released in 2011, the Armv8-A architecture added support for a 64-bit address space and 64-bit arithmetic with its new 32-bit fixed-length instruction set.[7] Some recent Arm CPUs have simultaneous multithreading (SMT) with e.g. Arm Neoverse E1 being able to execute two threads concurrently for improved aggregate throughput performance. Arm Cortex-A65AE for automotive applications is also a multithreaded processor, and has Dual Core Lock-Step for fault-tolerant designs (supporting Automotive Safety Integrity Level D, the highest level). The Neoverse N1 is designed for "as few as 8 cores" or "designs that scale from 64 to 128 N1 cores within a single coherent system".[8]

With over 130 billion Arm processors produced,[9][10][11][12] as of 2019, Arm is the most widely used instruction set architecture (ISA) and the ISA produced in the largest quantity.[13][4][14][15][16] Currently, the widely used Cortex cores, older "classic" cores, and specialized SecurCore cores variants are available for each of these to include or exclude optional capabilities.

History
Microprocessor-based system on a chip
Arm1 2nd processor for the BBC Micro

The British computer manufacturer Acorn Computers first developed the Acorn RISC Machine architecture (Arm)[17][18] in the 1980s to use in its personal computers. Its first Arm-based products were coprocessor modules for the 6502B based BBC Micro series of computers. After the successful BBC Micro computer, Acorn Computers considered how to move on from the relatively simple MOS Technology 6502 processor to address business markets like the one that was soon dominated by the IBM PC, launched in 1981. The Acorn Business Computer (ABC) plan required that a number of second processors be made to work with the BBC Micro platform, but processors such as the Motorola 68000 and National Semiconductor 32016 were considered unsuitable, and the 6502 was not powerful enough for a graphics-based user interface.[19]

According to Sophie Wilson, all the processors tested at that time performed about the same, with about a 4 Mbit/second bandwidth.[20]

After testing all available processors and finding them lacking, Acorn decided it needed a new architecture. Inspired by papers from the Berkeley RISC project, Acorn considered designing its own processor.[21] A visit to the Western Design Center in Phoenix, where the 6502 was being updated by what was effectively a single-person company, showed Acorn engineers Steve Furber and Sophie Wilson they did not need massive resources and state-of-the-art research and development facilities.[22]

Wilson developed the instruction set, writing a simulation of the processor in BBC BASIC that ran on a BBC Micro with a 6502 second processor.[23][24] This convinced Acorn engineers they were on the right track. Wilson approached Acorn's CEO, Hermann Hauser, and requested more resources. Hauser gave his approval and assembled a small team to implement Wilson's model in hardware.

Acorn RISC Machine: Arm2

The official Acorn RISC Machine project started in October 1983. They chose VLSI Technology as the silicon partner, as they were a source of ROMs and custom chips for Acorn. Wilson and Furber led the design. They implemented it with efficiency principles similar to the 6502.[25] A key design goal was achieving low-latency input/output (interrupt) handling like the 6502. The 6502's memory access architecture had let developers produce fast machines without costly direct memory access (DMA) hardware. The first samples of Arm silicon worked properly when first received and tested on 26 April 1985.[3]

The first Arm application was as a second processor for the BBC Micro, where it helped in developing simulation software to finish development of the support chips (VIDC, IOC, MEMC), and sped up the CAD software used in Arm2 development. Wilson subsequently rewrote BBC BASIC in Arm assembly language. The in-depth knowledge gained from designing the instruction set enabled the code to be very dense, making Arm BBC BASIC an extremely good test for any Arm emulator. The original aim of a principally Arm-based computer was achieved in 1987 with the release of the Acorn Archimedes.[26] In 1992, Acorn once more won the Queen's Award for Technology for the Arm.

The Arm2 featured a 32-bit data bus, 26-bit address space and 27 32-bit registers. Eight bits from the program counter register were available for other purposes; the top six bits (available because of the 26-bit address space) served as status flags, and the bottom two bits (available because the program counter was always word-aligned) were used for setting modes. The address bus was extended to 32 bits in the Arm6, but program code still had to lie within the first 64 MB of memory in 26-bit compatibility mode, due to the reserved bits for the status flags.[27] The Arm2 had a transistor count of just 30,000, compared to Motorola's six-year-older 68000 model with around 40,000.[28] Much of this simplicity came from the lack of microcode (which represents about one-quarter to one-third of the 68000) and from (like most CPUs of the day) not including any cache. This simplicity enabled low power consumption, yet better performance than the Intel 80286. A successor, Arm3, was produced with a 4 KB cache, which further improved performance.[29]

Advanced RISC Machines Ltd. – Arm6
Die of an Arm610 microprocessor

In the late 1980s, Apple Computer and VLSI Technology started working with Acorn on newer versions of the Arm core. In 1990, Acorn spun off the design team into a new company named Advanced RISC Machines Ltd.,[30][31][32] which became Arm Ltd when its parent company, Arm Holdings plc, floated on the London Stock Exchange and NASDAQ in 1998.[33] The new Apple-Arm work would eventually evolve into the Arm6, first released in early 1992. Apple used the Arm6-based Arm610 as the basis for their Apple Newton PDA.

Early licensees

In 1994, Acorn used the Arm610 as the main central processing unit (CPU) in their RiscPC computers. DEC licensed the Armv4 architecture and produced the StrongARM.[34] At 233 MHz, this CPU drew only one watt (newer versions draw far less). This work was later passed to Intel as part of a lawsuit settlement, and Intel took the opportunity to supplement their i960 line with the StrongArm. Intel later developed its own high performance implementation named XScale, which it has since sold to Marvell. Transistor count of the Arm core remained essentially the same throughout these changes; Arm2 had 30,000 transistors,[35] while Arm6 grew only to 35,000.[36]

Market share

In 2005, about 98% of all mobile phones sold used at least one Arm processor.[37] In 2010, producers of chips based on Arm architectures reported shipments of 6.1 billion Arm-based processors, representing 95% of smartphones, 35% of digital televisions and set-top boxes and 10% of mobile computers. In 2011, the 32-bit Arm architecture was the most widely used architecture in mobile devices and the most popular 32-bit one in embedded systems.[38] In 2013, 10 billion were produced[39] and "Arm-based chips are found in nearly 60 percent of the world's mobile devices".[40]

Licensing
Die of a STM32F103VGT6 ARM Cortex-M3 microcontroller with 1 MB flash memory by STMicroelectronics
See also: Arm Holdings § Licensees

Core licence

Arm Holdings' primary business is selling IP cores, which licensees use to create microcontrollers (MCUs), CPUs, and systems-on-chips based on those cores. The original design manufacturer combines the Arm core with other parts to produce a complete device, typically one that can be built in existing semiconductor fabrication plants (fabs) at low cost and still deliver substantial performance. The most successful implementation has been the Arm7TDMI with hundreds of millions sold. Atmel has been a precursor design center in the Arm7TDMI-based embedded system.

The Arm architectures used in smartphones, PDAs and other mobile devices range from Armv5 to Armv7-A, used in low-end and midrange devices, to Armv8-A used in current high-end devices.

In 2009, some manufacturers introduced netbooks based on Arm architecture CPUs, in direct competition with netbooks based on Intel Atom.[41]

Arm Holdings offers a variety of licensing terms, varying in cost and deliverables. Arm Holdings provides to all licensees an integratable hardware description of the Arm core as well as complete software development toolset (compiler, debugger, software development kit) and the right to sell manufactured silicon containing the Arm CPU.

SoC packages integrating Arm's core designs include Nvidia Tegra's first three generations, CSR plc's Quatro family, ST-Ericsson's Nova and NovaThor, Silicon Labs's Precision32 MCU, Texas Instruments's OMAP products, Samsung's Hummingbird and Exynos products, Apple's A4, A5, and A5X, and NXP's i.MX.

Fabless licensees, who wish to integrate an Arm core into their own chip design, are usually only interested in acquiring a ready-to-manufacture verified semiconductor intellectual property core. For these customers, Arm Holdings delivers a gate netlist description of the chosen Arm core, along with an abstracted simulation model and test programs to aid design integration and verification. More ambitious customers, including integrated device manufacturers (IDM) and foundry operators, choose to acquire the processor IP in synthesizable RTL (Verilog) form. With the synthesizable RTL, the customer has the ability to perform architectural level optimisations and extensions. This allows the designer to achieve exotic design goals not otherwise possible with an unmodified netlist (high clock speed, very low power consumption, instruction set extensions, etc.). While Arm Holdings does not grant the licensee the right to resell the Arm architecture itself, licensees may freely sell manufactured product such as chip devices, evaluation boards and complete systems. Merchant foundries can be a special case; not only are they allowed to sell finished silicon containing Arm cores, they generally hold the right to re-manufacture Arm cores for other customers.

Arm Holdings prices its IP based on perceived value. Lower performing Arm cores typically have lower licence costs than higher performing cores. In implementation terms, a synthesizable core costs more than a hard macro (blackbox) core. Complicating price matters, a merchant foundry that holds an Arm licence, such as Samsung or Fujitsu, can offer fab customers reduced licensing costs. In exchange for acquiring the Arm core through the foundry's in-house design services, the customer can reduce or eliminate payment of Arm's upfront licence fee.

Compared to dedicated semiconductor foundries (such as TSMC and UMC) without in-house design services, Fujitsu/Samsung charge two- to three-times more per manufactured wafer. For low to mid volume applications, a design service foundry offers lower overall pricing (through subsidisation of the licence fee). For high volume mass-produced parts, the long term cost reduction achievable through lower wafer pricing reduces the impact of Arm's NRE (Non-Recurring Engineering) costs, making the dedicated foundry a better choice.

Companies that have developed chips with cores designed by Arm Holdings include Amazon.com's Annapurna Labs subsidiary,[42] Analog Devices, Apple, AppliedMicro (now: MACOM Technology Solutions[43]), Atmel, Broadcom, Cavium, Cypress Semiconductor, Freescale Semiconductor (now NXP Semiconductors), Huawei, Intel, Maxim Integrated, Nvidia, NXP, Qualcomm, Renesas, Samsung Electronics, ST Microelectronics, Texas Instruments and Xilinx.

Built on Arm Cortex Technology licence

In February 2016, Arm announced the Built on Arm Cortex Technology licence, often shortened to Built on Cortex (BoC) licence. This licence allows companies to partner with Arm and make modifications to Arm Cortex designs. These design modifications will not be shared with other companies. These semi-custom core designs also have brand freedom, for example Kryo 280.

Companies that are current licensees of Built on Arm Cortex Technology include Qualcomm.[44]

Architectural licence

Companies can also obtain an Arm architectural licence for designing their own CPU cores using the Arm instruction sets. These cores must comply fully with the Arm architecture. Companies that have designed cores that implement an Arm architecture include Apple, AppliedMicro, Broadcom, Cavium (now: Marvell), Digital Equipment Corporation, Intel, Nvidia, Qualcomm, and Samsung Electronics.

Arm Flexible Access

On 16 July 2019, Arm announced Arm Flexible Access. Arm Flexible Access provides unlimited access to included Arm intellectual property (IP) for development. Per product licence fees are required once customers reaches foundry tapeout or prototyping.[45][46]

75% of Arm's most recent IP over the last two years are included in Arm Flexible Access. As of October 2019:

  • CPUs: Cortex-A5, Cortex-A7, Cortex-A32, Cortex-A34, Cortex-A35, Cortex-A53, Cortex-R5, Cortex-R8, Cortex-R52, Cortex-M0, Cortex-M0+, Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M23, Cortex-M33
  • GPUs: Mali-G52, Mali-G31. Includes Mali Driver Development Kits (DDK).
  • Interconnect: CoreLink NIC-400, CoreLink NIC-450, CoreLink CCI-400, CoreLink CCI-500, CoreLink CCI-550, ADB-400 AMBA, XHB-400 AXI-AHB
  • System Controllers: CoreLink GIC-400, CoreLink GIC-500, PL192 VIC, BP141 TrustZone Memory Wrapper, CoreLink TZC-400, CoreLink L2C-310, CoreLink MMU-500, BP140 Memory Interface
  • Security IP: CryptoCell-312, CryptoCell-712, TrustZone True Random Number Generator
  • Peripheral Controllers: PL011 UART, PL022 SPI, PL031 RTC
  • Debug & Trace: CoreSight SoC-400, CoreSight SDC-600, CoreSight STM-500, CoreSight System Trace Macrocell, CoreSight Trace Memory Controller
  • Design Kits: Corstone-101, Corstone-201
  • Physical IP: Artisan PIK for Cortex-M33 TSMC 22ULL including memory compilers, logic libraries, GPIOs and documentation
  • Tools & Materials: Socrates IP ToolingArm Design Studio, Virtual System Models
  • Support: Standard Arm Technical support, Arm online training, maintenance updates, credits towards onsite training and design reviews

Cores
Main article: List of ARM microarchitectures
Architecture Core
bit-width		 Cores Profile Refe-
rences
Arm Holdings Third-party
Armv1
32
ARM1
Classic
[a 1]
Armv2
32
ARM2, Arm250, ARM3Amber, STORM Open Soft Core[47]
Classic
[a 1]
Armv3
32
ARM6, ARM7
Classic
[a 2]
Armv4
32
Arm8StrongARM, FA526, ZAP Open Source Processor Core
Classic
[a 2]

[48]

Armv4T
32
ARM7TDMI, ARM9TDMI, SecurCore SC100
Classic
[a 2]
Armv5TE
32
ARM7EJ, ARM9E, ARM10EXScale, FA626TE, Feroceon, PJ1/Mohawk
Classic
Armv6
32
ARM11
Classic
Armv6-M
32
Arm Cortex-M0, ARM Cortex-M0+, ARM Cortex-M1, SecurCore SC000
Microcontroller
Armv7-M
32
Arm Cortex-M3, SecurCore SC300
Microcontroller
Armv7E-M
32
Arm Cortex-M4, ARM Cortex-M7
Microcontroller
Armv8-M
32
Arm Cortex-M23,[49] Arm Cortex-M33[50]
Microcontroller
[51]
Armv7-R
32
ARM Cortex-R4, ARM Cortex-R5, ARM Cortex-R7, ARM Cortex-R8
Real-time
Armv8-R
32
ARM Cortex-R52
Real-time
[52][53][54]
Armv7-A
32
ARM Cortex-A5, ARM Cortex-A7, ARM Cortex-A8, ARM Cortex-A9, ARM Cortex-A12, ARM Cortex-A15, ARM Cortex-A17Qualcomm Scorpion/Krait, PJ4/Sheeva, Apple Swift
Application
Armv8-A
32
ARM Cortex-A32[55]
Application
64/32
ARM Cortex-A35,[56] ARM Cortex-A53, ARM Cortex-A57,[57] ARM Cortex-A72,[58] ARM Cortex-A73[59]X-Gene, Nvidia Denver 1/2, Cavium ThunderX, AMD K12, Apple Cyclone/Typhoon/Twister/Hurricane/Zephyr, Qualcomm Kryo, Samsung M1/M2 ("Mongoose") /M3 ("Meerkat")
Application
[60][61][62][63][64]

[65]

64
ARM Cortex-A34[66]
Application
Armv8.1-A
64/32
TBACavium ThunderX2
Application
[67]
Armv8.2-A
64/32
ARM Cortex-A55,[68] ARM Cortex-A75,[69] ARM Cortex-A76,[70] ARM Cortex-A77, ARM Cortex-A78, ARM Cortex-X1, Arm Neoverse N1 Nvidia Carmel, Samsung M4 ("Cheetah"), Fujitsu A64FX (Armv8 SVE 512-bit)
Application
[71][72]

[73]

64
Arm Cortex-A65, Arm Neoverse E1 with simultaneous multithreading (SMT), Arm Cortex-A65AE[74] (also having e.g. Armv8.4 Dot Product; made for safety critical tasks such as advanced driver-assistance systems (ADAS))Apple Monsoon/Mistral (September 2017)
Application
Armv8.3-A
64/32
TBA
Application
64
TBAApple Vortex/Tempest

Marvell ThunderX3 (v8.3+)[75]
Application
Armv8.4-A
64/32
TBA
Application
64
TBAApple Lightning/Thunder
Application

Armv8.5-A
64/32
TBA
Application

Armv8.6-A
64/32
TBA
Application
  1. Although most datapaths and CPU registers in the early ARM processors were 32-bit, addressable memory was limited to 26 bits; with upper bits, then, used for status flags in the program counter register.
  2. ARMv3 included a compatibility mode to support the 26-bit addresses of earlier versions of the architecture. This compatibility mode optional in ARMv4, and removed entirely in ARMv5.

Arm Holdings provides a list of vendors who implement Arm cores in their design (application specific standard products (ASSP), microprocessor and microcontrollers).[76]

Example applications of Arm cores
Tronsmart MK908, a Rockchip-based quad-core Android "mini PC", with a microSD card next to it for a size comparison
Main article: List of applications of ARM cores

Arm cores are used in a number of products, particularly PDAs and smartphones. Some computing examples are Microsoft's first generation Surface and Surface 2, Apple's iPads and Asus's Eee Pad Transformer tablet computers, and several Chromebook laptops. Others include Apple's iPhone smartphone and iPod portable media player, Canon PowerShot digital cameras, Nintendo Switch hybrid and 3DS handheld game consoles, and TomTom turn-by-turn navigation systems.

In 2005, Arm Holdings took part in the development of Manchester University's computer SpiNNaker, which used Arm cores to simulate the human brain.[77]

Arm chips are also used in Raspberry Pi, BeagleBoard, BeagleBone, PandaBoard and other single-board computers, because they are very small, inexpensive and consume very little power.

32-bit architecture
An Armv7 was used to power older versions of the popular Raspberry Pi single board computers like this Raspberry Pi 2 from 2015.
An Armv7 is also used to power the CuBox family of single board computers.
See also: Comparison of ARMv7-A cores

The 32-bit Arm architecture, such as Armv7-A (implementing AArch32; see section on ARMv8 for more on it), was the most widely used architecture in mobile devices as of 2011.[38]

Since 1995, the Arm Architecture Reference Manual[78] has been the primary source of documentation on the Arm processor architecture and instruction set, distinguishing interfaces that all Arm processors are required to support (such as instruction semantics) from implementation details that may vary. The architecture has evolved over time, and version seven of the architecture, Armv7, defines three architecture "profiles":

  • A-profile, the "Application" profile, implemented by 32-bit cores in the Cortex-A series and by some non-Arm cores
  • R-profile, the "Real-time" profile, implemented by cores in the Cortex-R series
  • M-profile, the "Microcontroller" profile, implemented by most cores in the Cortex-M series

Although the architecture profiles were first defined for Armv7, Arm subsequently defined the Armv6-M architecture (used by the Cortex M0/M0+/M1) as a subset of the Armv7-M profile with fewer instructions.

CPU modes

Except in the M-profile, the 32-bit Arm architecture specifies several CPU modes, depending on the implemented architecture features. At any moment in time, the CPU can be in only one mode, but it can switch modes due to external events (interrupts) or programmatically.[79]

  • User mode: The only non-privileged mode.
  • FIQ mode: A privileged mode that is entered whenever the processor accepts a fast interrupt request.
  • IRQ mode: A privileged mode that is entered whenever the processor accepts an interrupt.
  • Supervisor (svc) mode: A privileged mode entered whenever the CPU is reset or when an SVC instruction is executed.
  • Abort mode: A privileged mode that is entered whenever a prefetch abort or data abort exception occurs.
  • Undefined mode: A privileged mode that is entered whenever an undefined instruction exception occurs.
  • System mode (Armv4 and above): The only privileged mode that is not entered by an exception. It can only be entered by executing an instruction that explicitly writes to the mode bits of the Current Program Status Register (CPSR) from another privileged mode (not from user mode).
  • Monitor mode (Armv6 and Armv7 Security Extensions, Armv8 EL3): A monitor mode is introduced to support TrustZone extension in Arm cores.
  • Hyp mode (Armv7 Virtualization Extensions, Armv8 EL2): A hypervisor mode that supports Popek and Goldberg virtualization requirements for the non-secure operation of the CPU.[80][81]
  • Thread mode (Armv6-M, Armv7-M, Armv8-M): A mode which can be specified as either privileged or unprivileged. Whether the Main Stack Pointer (MSP) or Process Stack Pointer (PSP) is used can also be specified in CONTROL register with privileged access. This mode is designed for user tasks in RTOS environment but it's typically used in bare-metal for super-loop.
  • Handler mode (Armv6-M, Armv7-M, Armv8-M): A mode dedicated for exception handling (except the RESET which are handled in Thread mode). Handler mode always uses MSP and works in privileged level.

Instruction set

The original (and subsequent) Arm implementation was hardwired without microcode, like the much simpler 8-bit 6502 processor used in prior Acorn microcomputers.

The 32-bit Arm architecture (and the 64-bit architecture for the most part) includes the following RISC features:

  • Load/store architecture.
  • No support for unaligned memory accesses in the original version of the architecture. Armv6 and later, except some microcontroller versions, support unaligned accesses for half-word and single-word load/store instructions with some limitations, such as no guaranteed atomicity.[82][83]
  • Uniform 16 × 32-bit register file (including the program counter, stack pointer and the link register).
  • Fixed instruction width of 32 bits to ease decoding and pipelining, at the cost of decreased code density. Later, the Thumb instruction set added 16-bit instructions and increased code density.
  • Mostly single clock-cycle execution.

To compensate for the simpler design, compared with processors like the Intel 80286 and Motorola 68020, some additional design features were used:

  • Conditional execution of most instructions reduces branch overhead and compensates for the lack of a branch predictor in early chips.
  • Arithmetic instructions alter condition codes only when desired.
  • 32-bit barrel shifter can be used without performance penalty with most arithmetic instructions and address calculations.
  • Has powerful indexed addressing modes.
  • A link register supports fast leaf function calls.
  • A simple, but fast, 2-priority-level interrupt subsystem has switched register banks.

Arithmetic instructions

Arm includes integer arithmetic operations for add, subtract, and multiply; some versions of the architecture also support divide operations.

Arm supports 32-bit × 32-bit multiplies with either a 32-bit result or 64-bit result, though Cortex-M0 / M0+ / M1 cores don't support 64-bit results.[84] Some Arm cores also support 16-bit × 16-bit and 32-bit × 16-bit multiplies.

The divide instructions are only included in the following Arm architectures:

  • Armv7-M and Armv7E-M architectures always include divide instructions.[85]
  • Armv7-R architecture always includes divide instructions in the Thumb instruction set, but optionally in its 32-bit instruction set.[86]
  • Armv7-A architecture optionally includes the divide instructions. The instructions might not be implemented, or implemented only in the Thumb instruction set, or implemented in both the Thumb and Arm instruction sets, or implemented if the Virtualization Extensions are included.[86]

Registers
Registers across CPU modes
usrsyssvcabtundirqfiq
R0
R1
R2
R3
R4
R5
R6
R7
R8R8_fiq
R9R9_fiq
R10R10_fiq
R11R11_fiq
R12R12_fiq
R13R13_svcR13_abtR13_undR13_irqR13_fiq
R14R14_svcR14_abtR14_undR14_irqR14_fiq
R15
CPSR
SPSR_svcSPSR_abtSPSR_undSPSR_irqSPSR_fiq

Registers R0 through R7 are the same across all CPU modes; they are never banked.

Registers R8 through R12 are the same across all CPU modes except FIQ mode. FIQ mode has its own distinct R8 through R12 registers.

R13 and R14 are banked across all privileged CPU modes except system mode. That is, each mode that can be entered because of an exception has its own R13 and R14. These registers generally contain the stack pointer and the return address from function calls, respectively.

Aliases:

  • R13 is also referred to as SP, the Stack Pointer.
  • R14 is also referred to as LR, the Link Register.
  • R15 is also referred to as PC, the Program Counter.

The Current Program Status Register (CPSR) has the following 32 bits.[87]

  • M (bits 0–4) is the processor mode bits.
  • T (bit 5) is the Thumb state bit.
  • F (bit 6) is the FIQ disable bit.
  • I (bit 7) is the IRQ disable bit.
  • A (bit 8) is the imprecise data abort disable bit.
  • E (bit 9) is the data endianness bit.
  • IT (bits 10–15 and 25–26) is the if-then state bits.
  • GE (bits 16–19) is the greater-than-or-equal-to bits.
  • DNM (bits 20–23) is the do not modify bits.
  • J (bit 24) is the Java state bit.
  • Q (bit 27) is the sticky overflow bit.
  • V (bit 28) is the overflow bit.
  • C (bit 29) is the carry/borrow/extend bit.
  • Z (bit 30) is the zero bit.
  • N (bit 31) is the negative/less than bit.

Conditional execution

Almost every Arm instruction has a conditional execution feature called predication, which is implemented with a 4-bit condition code selector (the predicate). To allow for unconditional execution, one of the four-bit codes causes the instruction to be always executed. Most other CPU architectures only have condition codes on branch instructions.[88]

Though the predicate takes up four of the 32 bits in an instruction code, and thus cuts down significantly on the encoding bits available for displacements in memory access instructions, it avoids branch instructions when generating code for small if statements. Apart from eliminating the branch instructions themselves, this preserves the fetch/decode/execute pipeline at the cost of only one cycle per skipped instruction.

An algorithm that provides a good example of conditional execution is the subtraction-based Euclidean algorithm for computing the greatest common divisor. In the C programming language, the algorithm can be written as:

int gcd(int a, int b) {
  while (a != b)  // We enter the loop when a<b or a>b, but not when a==b
    if (a > b)   // When a>b we do this
      a -= b;
    else         // When a<b we do that (no if(a<b) needed since a!=b is checked in while condition)
      b -= a;
  return a;
}

The same algorithm can be rewritten in a way closer to target Arm instructions as:

loop:
    // Compare a and b
    GT = a > b;
    LT = a < b;
    NE = a != b;

    // Perform operations based on flag results
    if(GT) a -= b;    // Subtract *only* if greater-than
    if(LT) b -= a;    // Subtract *only* if less-than
    if(NE) goto loop; // Loop *only* if compared values were not equal
    return a;

and coded in assembly language as:

; assign a to register r0, b to r1
loop:   CMP    r0, r1       ; set condition "NE" if (a != b),
                            ;               "GT" if (a > b),
                            ;            or "LT" if (a < b)
        SUBGT  r0, r0, r1   ; if "GT" (Greater Than), a = a-b;
        SUBLT  r1, r1, r0   ; if "LT" (Less Than), b = b-a;
        BNE  loop           ; if "NE" (Not Equal), then loop
        B    lr             ; if the loop is not entered, we can safely return

which avoids the branches around the then and else clauses. If r0 and r1 are equal then neither of the SUB instructions will be executed, eliminating the need for a conditional branch to implement the while check at the top of the loop, for example had SUBLE (less than or equal) been used.

One of the ways that Thumb code provides a more dense encoding is to remove the four-bit selector from non-branch instructions.

Other features

Another feature of the instruction set is the ability to fold shifts and rotates into the "data processing" (arithmetic, logical, and register-register move) instructions, so that, for example, the C statement

a += (j << 2);

could be rendered as a single-word, single-cycle instruction:[89]

ADD  Ra, Ra, Rj, LSL #2

This results in the typical Arm program being denser than expected with fewer memory accesses; thus the pipeline is used more efficiently.

The Arm processor also has features rarely seen in other RISC architectures, such as PC-relative addressing (indeed, on the 32-bit[1] Arm the PC is one of its 16 registers) and pre- and post-increment addressing modes.

The Arm instruction set has increased over time. Some early Arm processors (before Arm7TDMI), for example, have no instruction to store a two-byte quantity.

Pipelines and other implementation issues

The Arm7 and earlier implementations have a three-stage pipeline; the stages being fetch, decode and execute. Higher-performance designs, such as the Arm9, have deeper pipelines: Cortex-A8 has thirteen stages. Additional implementation changes for higher performance include a faster adder and more extensive branch prediction logic. The difference between the Arm7DI and Arm7DMI cores, for example, was an improved multiplier; hence the added "M".

Coprocessors

The Arm architecture (pre-Armv8) provides a non-intrusive way of extending the instruction set using "coprocessors" that can be addressed using MCR, MRC, MRRC, MCRR and similar instructions. The coprocessor space is divided logically into 16 coprocessors with numbers from 0 to 15, coprocessor 15 (cp15) being reserved for some typical control functions like managing the caches and MMU operation on processors that have one.

In Arm-based machines, peripheral devices are usually attached to the processor by mapping their physical registers into Arm memory space, into the coprocessor space, or by connecting to another device (a bus) that in turn attaches to the processor. Coprocessor accesses have lower latency, so some peripherals—for example, an XScale interrupt controller—are accessible in both ways: through memory and through coprocessors.

In other cases, chip designers only integrate hardware using the coprocessor mechanism. For example, an image processing engine might be a small Arm7TDMI core combined with a coprocessor that has specialised operations to support a specific set of HDTV transcoding primitives.

Debugging

All modern Arm processors include hardware debugging facilities, allowing software debuggers to perform operations such as halting, stepping, and breakpointing of code starting from reset. These facilities are built using JTAG support, though some newer cores optionally support Arm's own two-wire "SWD" protocol. In Arm7TDMI cores, the "D" represented JTAG debug support, and the "I" represented presence of an "EmbeddedICE" debug module. For Arm7 and Arm9 core generations, EmbeddedICE over JTAG was a de facto debug standard, though not architecturally guaranteed.

The Armv7 architecture defines basic debug facilities at an architectural level. These include breakpoints, watchpoints and instruction execution in a "Debug Mode"; similar facilities were also available with EmbeddedICE. Both "halt mode" and "monitor" mode debugging are supported. The actual transport mechanism used to access the debug facilities is not architecturally specified, but implementations generally include JTAG support.

There is a separate Arm "CoreSight" debug architecture, which is not architecturally required by Armv7 processors.

Debug Access Port

The Debug Access Port (DAP) is an implementation of an Arm Debug Interface.[90] There are two different supported implementations, the Serial Wire JTAG Debug Port (SWJ-DP) and the Serial Wire Debug Port (SW-DP).[91] CMSIS-DAP is a standard interface that describes how various debugging software on a host PC can communicate over USB to firmware running on a hardware debugger, which in turn talks over SWD or JTAG to a CoreSight-enabled Arm Cortex CPU.[92][93][94][95]

DSP enhancement instructions

To improve the Arm architecture for digital signal processing and multimedia applications, DSP instructions were added to the set.[96] These are signified by an "E" in the name of the Armv5TE and Armv5TEJ architectures. E-variants also imply T, D, M, and I.

The new instructions are common in digital signal processor (DSP) architectures. They include variations on signed multiply–accumulate, saturated add and subtract, and count leading zeros.

SIMD extensions for multimedia

Introduced in the Armv6 architecture, this was a precursor to Advanced SIMD, also known as Neon.[97]

Jazelle
Main article: Jazelle

Jazelle DBX (Direct Bytecode eXecution) is a technique that allows Java bytecode to be executed directly in the Arm architecture as a third execution state (and instruction set) alongside the existing Arm and Thumb-mode. Support for this state is signified by the "J" in the Armv5TEJ architecture, and in Arm9EJ-S and Arm7EJ-S core names. Support for this state is required starting in Armv6 (except for the Armv7-M profile), though newer cores only include a trivial implementation that provides no hardware acceleration.

Thumb

To improve compiled code-density, processors since the Arm7TDMI (released in 1994[98]) have featured the Thumb instruction set, which have their own state. (The "T" in "TDMI" indicates the Thumb feature.) When in this state, the processor executes the Thumb instruction set, a compact 16-bit encoding for a subset of the Arm instruction set.[99] Most of the Thumb instructions are directly mapped to normal Arm instructions. The space-saving comes from making some of the instruction operands implicit and limiting the number of possibilities compared to the Arm instructions executed in the Arm instruction set state.

In Thumb, the 16-bit opcodes have less functionality. For example, only branches can be conditional, and many opcodes are restricted to accessing only half of all of the CPU's general-purpose registers. The shorter opcodes give improved code density overall, even though some operations require extra instructions. In situations where the memory port or bus width is constrained to less than 32 bits, the shorter Thumb opcodes allow increased performance compared with 32-bit Arm code, as less program code may need to be loaded into the processor over the constrained memory bandwidth.

Unlike processor architectures with variable length (16- or 32-bit) instructions, such as the Cray-1 and Hitachi SuperH, the Arm and Thumb instruction sets exist independently of each other. Embedded hardware, such as the Game Boy Advance, typically have a small amount of RAM accessible with a full 32-bit datapath; the majority is accessed via a 16-bit or narrower secondary datapath. In this situation, it usually makes sense to compile Thumb code and hand-optimise a few of the most CPU-intensive sections using full 32-bit Arm instructions, placing these wider instructions into the 32-bit bus accessible memory.

The first processor with a Thumb instruction decoder was the Arm7TDMI. All Arm9 and later families, including XScale, have included a Thumb instruction decoder. It includes instructions adopted from the Hitachi SuperH (1992), which was licensed by Arm.[100] Arm's smallest processor families (Cortex M0 and M1) implement only the 16-bit Thumb instruction set for maximum performance in lowest cost applications.

Thumb-2

Thumb-2 technology was introduced in the Arm1156 core, announced in 2003. Thumb-2 extends the limited 16-bit instruction set of Thumb with additional 32-bit instructions to give the instruction set more breadth, thus producing a variable-length instruction set. A stated aim for Thumb-2 was to achieve code density similar to Thumb with performance similar to the Arm instruction set on 32-bit memory.

Thumb-2 extends the Thumb instruction set with bit-field manipulation, table branches and conditional execution. At the same time, the Arm instruction set was extended to maintain equivalent functionality in both instruction sets. A new "Unified Assembly Language" (UAL) supports generation of either Thumb or Arm instructions from the same source code; versions of Thumb seen on Armv7 processors are essentially as capable as Arm code (including the ability to write interrupt handlers). This requires a bit of care, and use of a new "IT" (if-then) instruction, which permits up to four successive instructions to execute based on a tested condition, or on its inverse. When compiling into Arm code, this is ignored, but when compiling into Thumb it generates an actual instruction. For example:

; if (r0 == r1)
CMP r0, r1
ITE EQ        ; ARM: no code ... Thumb: IT instruction
; then r0 = r2;
MOVEQ r0, r2  ; ARM: conditional; Thumb: condition via ITE 'T' (then)
; else r0 = r3;
MOVNE r0, r3  ; ARM: conditional; Thumb: condition via ITE 'E' (else)
; recall that the Thumb MOV instruction has no bits to encode "EQ" or "NE".

All Armv7 chips support the Thumb instruction set. All chips in the Cortex-A series, Cortex-R series, and Arm11 series support both "Arm instruction set state" and "Thumb instruction set state", while chips in the Cortex-M series support only the Thumb instruction set.[101][102][103]

Thumb Execution Environment (ThumbEE)

ThumbEE (erroneously called Thumb-2EE in some Arm documentation), which was marketed as Jazelle RCT (Runtime Compilation Target), was announced in 2005, first appearing in the Cortex-A8 processor. ThumbEE is a fourth instruction set state, making small changes to the Thumb-2 extended instruction set. These changes make the instruction set particularly suited to code generated at runtime (e.g. by JIT compilation) in managed Execution Environments. ThumbEE is a target for languages such as Java, C#, Perl, and Python, and allows JIT compilers to output smaller compiled code without impacting performance.

New features provided by ThumbEE include automatic null pointer checks on every load and store instruction, an instruction to perform an array bounds check, and special instructions that call a handler. In addition, because it utilises Thumb-2 technology, ThumbEE provides access to registers r8-r15 (where the Jazelle/DBX Java VM state is held).[104] Handlers are small sections of frequently called code, commonly used to implement high level languages, such as allocating memory for a new object. These changes come from repurposing a handful of opcodes, and knowing the core is in the new ThumbEE state.

On 23 November 2011, Arm Holdings deprecated any use of the ThumbEE instruction set,[105] and Armv8 removes support for ThumbEE.

Floating-point (VFP)

VFP (Vector Floating Point) technology is an floating-point unit (FPU) coprocessor extension to the Arm architecture[106] (implemented differently in Armv8 – coprocessors not defined there). It provides low-cost single-precision and double-precision floating-point computation fully compliant with the ANSI/IEEE Std 754-1985 Standard for Binary Floating-Point Arithmetic. VFP provides floating-point computation suitable for a wide spectrum of applications such as PDAs, smartphones, voice compression and decompression, three-dimensional graphics and digital audio, printers, set-top boxes, and automotive applications. The VFP architecture was intended to support execution of short "vector mode" instructions but these operated on each vector element sequentially and thus did not offer the performance of true single instruction, multiple data (SIMD) vector parallelism. This vector mode was therefore removed shortly after its introduction,[107] to be replaced with the much more powerful Neon Advanced SIMD unit.

Some devices such as the Arm Cortex-A8 have a cut-down VFPLite module instead of a full VFP module, and require roughly ten times more clock cycles per float operation.[108] Pre-Armv8 architecture implemented floating-point/SIMD with the coprocessor interface. Other floating-point and/or SIMD units found in Arm-based processors using the coprocessor interface include FPA, FPE, iwMMXt, some of which were implemented in software by trapping but could have been implemented in hardware. They provide some of the same functionality as VFP but are not opcode-compatible with it.

VFPv1
Obsolete
VFPv2
An optional extension to the Arm instruction set in the Armv5TE, Armv5TEJ and Armv6 architectures. VFPv2 has 16 64-bit FPU registers.
VFPv3 or VFPv3-D32
Implemented on most Cortex-A8 and A9 Armv7 processors. It is backwards compatible with VFPv2, except that it cannot trap floating-point exceptions. VFPv3 has 32 64-bit FPU registers as standard, adds VCVT instructions to convert between scalar, float and double, adds immediate mode to VMOV such that constants can be loaded into FPU registers.
VFPv3-D16
As above, but with only 16 64-bit FPU registers. Implemented on Cortex-R4 and R5 processors and the Tegra 2 (Cortex-A9).
VFPv3-F16
Uncommon; it supports IEEE754-2008 half-precision (16-bit) floating point as a storage format.
VFPv4 or VFPv4-D32
Implemented on the Cortex-A12 and A15 Armv7 processors, Cortex-A7 optionally has VFPv4-D32 in the case of an FPU with Neon.[109] VFPv4 has 32 64-bit FPU registers as standard, adds both half-precision support as a storage format and fused multiply-accumulate instructions to the features of VFPv3.
VFPv4-D16
As above, but it has only 16 64-bit FPU registers. Implemented on Cortex-A5 and A7 processors (in case of an FPU without Neon[109]).
VFPv5-D16-M
Implemented on Cortex-M7 when single and double-precision floating-point core option exists.

In Debian GNU/Linux, and derivatives such as Ubuntu and Linux Mint, armhf (Arm hard float) refers to the Armv7 architecture including the additional VFP3-D16 floating-point hardware extension (and Thumb-2) above. Software packages and cross-compiler tools use the armhf vs. arm/armel suffixes to differentiate.[110]

Advanced SIMD (Neon)

The Advanced SIMD extension (aka Neon or "MPE" Media Processing Engine) is a combined 64- and 128-bit SIMD instruction set that provides standardized acceleration for media and signal processing applications. Neon is included in all Cortex-A8 devices, but is optional in Cortex-A9 devices.[111] Neon can execute MP3 audio decoding on CPUs running at 10 MHz, and can run the GSM adaptive multi-rate (AMR) speech codec at 13 MHz. It features a comprehensive instruction set, separate register files, and independent execution hardware.[112] Neon supports 8-, 16-, 32-, and 64-bit integer and single-precision (32-bit) floating-point data and SIMD operations for handling audio and video processing as well as graphics and gaming processing. In Neon, the SIMD supports up to 16 operations at the same time. The Neon hardware shares the same floating-point registers as used in VFP. Devices such as the Arm Cortex-A8 and Cortex-A9 support 128-bit vectors, but will execute with 64 bits at a time,[108] whereas newer Cortex-A15 devices can execute 128 bits at a time.[113][114]

A quirk of Neon in Armv7 devices is that it flushes all subnormal numbers to zero, and as a result the GCC compiler will not use it unless -funsafe-math-optimizations, which allows losing denormals, is turned on. "Enhanced" Neon defined since Armv8 does not have this quirk, but as of GCC 8.2 the same flag is still required to enable Neon instructions.[115] On the other hand, GCC does consider Neon safe on AArch64 for Armv8.

ProjectNe10 is Arm's first open-source project (from its inception; while they acquired an older project, now known as Mbed TLS). The Ne10 library is a set of common, useful functions written in both Neon and C (for compatibility). The library was created to allow developers to use Neon optimisations without learning Neon, but it also serves as a set of highly optimised Neon intrinsic and assembly code examples for common DSP, arithmetic, and image processing routines. The source code is available on GitHub.[116]

Arm Helium technology

Helium adds more than 150 scalar and vector instructions.[117]

Security extensions

TrustZone (for Cortex-A profile)

The Security Extensions, marketed as TrustZone Technology, is in Armv6KZ and later application profile architectures. It provides a low-cost alternative to adding another dedicated security core to an SoC, by providing two virtual processors backed by hardware based access control. This lets the application core switch between two states, referred to as worlds (to reduce confusion with other names for capability domains), in order to prevent information from leaking from the more trusted world to the less trusted world. This world switch is generally orthogonal to all other capabilities of the processor, thus each world can operate independently of the other while using the same core. Memory and peripherals are then made aware of the operating world of the core and may use this to provide access control to secrets and code on the device.[118]

Typically, a rich operating system is run in the less trusted world, with smaller security-specialized code in the more trusted world, aiming to reduce the attack surface. Typical applications include DRM functionality for controlling the use of media on Arm-based devices,[119] and preventing any unapproved use of the device.

In practice, since the specific implementation details of proprietary TrustZone implementations have not been publicly disclosed for review, it is unclear what level of assurance is provided for a given threat model, but they are not immune from attack.[120][121]

Open Virtualization[122] is an open source implementation of the trusted world architecture for TrustZone.

AMD has licensed and incorporated TrustZone technology into its Secure Processor Technology.[123] Enabled in some but not all products, AMD's APUs include a Cortex-A5 processor for handling secure processing.[124][125][126] In fact, the Cortex-A5 TrustZone core had been included in earlier AMD products, but was not enabled due to time constraints.[125]

Samsung Knox uses TrustZone for purposes such as detecting modifications to the kernel.[127]

TrustZone for Armv8-M (for Cortex-M profile)

The Security Extension, marketed as TrustZone for Armv8-M Technology, was introduced in the Armv8-M architecture. While containing similar concepts to TrustZone for Armv8-A, it has a different architectural design, as world switching is performed using branch instructions instead of using exceptions. It also supports safe interleaved interrupt handling from either world regardless of the current security state. Together these features provide low latency calls to the secure world and responsive interrupt handling. Arm provides a reference stack of secure world code in the form of Trusted Firmware for M and PSA Certified.

No-execute page protection

As of Armv6, the Arm architecture supports no-execute page protection, which is referred to as XN, for eXecute Never.[128]

Large Physical Address Extension (LPAE)

The Large Physical Address Extension (LPAE), which extends the physical address size from 32 bits to 40 bits, was added to the Armv7-A architecture in 2011.[129] Physical address size is larger, 44 bits, in Cortex-A75 and Cortex-A65AE.[130]

Armv8-R and Armv8-M

The Armv8-R and Armv8-M architectures, announced after the Armv8-A architecture, share some features with Armv8-A, but don't include any 64-bit AArch64 instructions.

Armv8.1-M

The Armv8.1-M architecture, announced in February 2019, is an enhancement of the Armv8-M architecture. It brings new features including:

  • A new vector instruction set extension. The M-Profile Vector Extension (MVE), or Helium, is for signal processing and machine learning applications.
  • Additional instruction set enhancements for loops and branches (Low Overhead Branch Extension).
  • Instructions for half-precision floating-point support.
  • Instruction set enhancement for TrustZone management for Floating Point Unit (FPU).
  • New memory attribute in the Memory Protection Unit (MPU).
  • Enhancements in debug including Performance Monitoring Unit (PMU), Unprivileged Debug Extension, and additional debug support focus on signal processing application developments.
  • Reliability, Availability and Serviceability (RAS) extension.

64/32-bit architecture
Main article: AArch64
Armv8-A Platform with Cortex A57/A53 MPCore big.LITTLE CPU chip

Armv8-A
See also: Comparison of ARMv8-A cores

Announced in October 2011,[7] Armv8-A (often called Armv8 while the Armv8-R is also available) represents a fundamental change to the Arm architecture. It adds an optional 64-bit architecture (e.g. Cortex-A32 is a 32-bit Armv8-A CPU[131] while most Armv8-A CPUs support 64-bit, unlike all Armv8-R), named "AArch64", and the associated new "A64" instruction set. AArch64 provides user-space compatibility with Armv7-A, the 32-bit architecture, therein referred to as "AArch32" and the old 32-bit instruction set, now named "A32". The Thumb instruction set is referred to as "T32" and has no 64-bit counterpart. Armv8-A allows 32-bit applications to be executed in a 64-bit OS, and a 32-bit OS to be under the control of a 64-bit hypervisor.[1] Arm announced their Cortex-A53 and Cortex-A57 cores on 30 October 2012.[57] Apple was the first to release an Armv8-A compatible core (Apple A7) in a consumer product (iPhone 5S). AppliedMicro, using an FPGA, was the first to demo Armv8-A.[132] The first Armv8-A SoC from Samsung is the Exynos 5433 used in the Galaxy Note 4, which features two clusters of four Cortex-A57 and Cortex-A53 cores in a big.LITTLE configuration; but it will run only in AArch32 mode.[133]

To both AArch32 and AArch64, Armv8-A makes VFPv3/v4 and advanced SIMD (Neon) standard. It also adds cryptography instructions supporting AES, SHA-1/SHA-256 and finite field arithmetic.[134] AArch64 was introduced in ArmV8-A and its subsequent revision. AArch64 is not included in the 32-bit Armv8-R and Armv8-M architectures.

Platform Security Architecture

Platform Security Architecture (PSA)[135] is an architecture-agnostic security framework and evaluation scheme, intended to help secure Internet of Things (IoT) devices built on system-on-a-chip (SoC) processors. It was introduced by Arm in 2017[136] at the annual TechCon event[137] and will be first used on Arm Cortex-M processor cores intended for microcontroller use. The PSA includes freely available threat models and security analyses that demonstrate the process for deciding on security features[138] in common IoT products. The PSA also provides freely downloadable application programming interface (API) packages,[139] architectural specifications, open-source firmware implementations, and related test suites. PSA Certified[140] offers a multi-level security evaluation scheme for chip vendors, OS providers and IoT device makers.

Operating system support

32-bit operating systems
Android, a popular operating system which is primarily used on the Arm architecture.

Historical operating systems

The first 32-bit Arm-based personal computer, the Acorn Archimedes, ran an interim operating system called Arthur, which evolved into RISC OS, used on later Arm-based systems from Acorn and other vendors. Some Acorn machines also had a Unix port called RISC iX. (Neither is to be confused with RISC/os, a contemporary Unix variant for the MIPS architecture.)

Embedded operating systems

The 32-bit Arm architecture is supported by a large number of embedded and real-time operating systems, including:

Mobile device operating systems

The 32-bit Arm architecture is the primary hardware environment for most mobile device operating systems such as:

Previously, but now discontinued:

  • iOS 10 and earlier

Desktop/server operating systems

The 32-bit Arm architecture is supported by RISC OS and by multiple Unix-like operating systems including:

64-bit operating systems

Embedded operating systems

Mobile device operating systems

Desktop/server operating systems

Porting to 32- or 64-bit Arm operating systems

Windows applications recompiled for Arm and linked with Winelib – from the Wine project – can run on 32-bit or 64-bit Arm in Linux, FreeBSD or other compatible operating systems.[167][168] x86 binaries, e.g. when not specially compiled for Arm, have been demonstrated on Arm using QEMU with Wine (on Linux and more), but do not work at full speed or same capability as with Winelib.

gollark: Also, Epicbot [REDACTED] class-84 sentient AI.
gollark: * hm
gollark: I forgot whether I made ++tel unlink available to server moderators too, him.
gollark: PRs welcome!
gollark: PRs welcome!

See also

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Further reading
See also: List of books about ARM Cortex-M
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