ARM Cortex-A78

The ARM Cortex-A78 is a microarchitecture implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin centre, set to be distributed amongst high-end devices in 2020–2021.[1]

ARM Cortex-A78

General Info
Launched	2020
Designed by	ARM Holdings
Max. CPU clock rate	to 3.0 GHz in phones and 3.3 GHz in tablets/laptops
Cache
L1 cache	32–64 KB (Parity Neon SIMD engine, Floating point unit)
L2 cache	256–512 (Private L2 ECC) KiB
L3 cache	Optional, 512KB to 4MB (up to 8 MB) with Cortex-X1
Architecture and classification
Architecture	ARMv8-A
Microarchitecture	ARM Cortex-A78
Instruction set	ARMv8-A
Extensions	ARMv8.1-A, ARMv8.2-A, Cryptography, RAS, ARMv8.3-A LDAPR instructions
Physical specifications
Cores	1–4 per cluster
Products, models, variants
Product code name(s)	Hercules
Variant(s)	ARM Cortex-X1
History
Predecessor	ARM Cortex-A77

Design

The ARM Cortex-A78 is the successor to the ARM Cortex-A77. It can be paired with the ARM Cortex-X1 and/or ARM Cortex-A55 CPUs in a DynamIQ configuration to deliver both performance and efficiency. The processor also has 50% more energy savings than that of its predecessor.

The Cortex-A78 is a 4-wide decode out-of-order superscalar design with a 1.5K macro-OP (MOPs) cache. It can fetch 4 instructions and 6 Mops per cycle. And rename and dispatch 6 Mops, and 13 µops per cycle. The out-of-order window size is 160 entries. And the backend is 13 execution ports with a pipeline depth of 13 stages and the execution latencies consists of 10 stages.[2][3]

The processor is built on a standard Cortex-A roadmap and offers a 2.1 GHz (5 nm) chipset which makes it better than its predecessor in the following ways:

• 7% better performance
• 4% lower power consumption
• 5% smaller, meaning 15% more area serving for a quad-core cluster, extra GPU, NPU

There is also extended scalability with extra support from Dynamic Shared Unit for DynamIQ on the chipset. A smaller 32 KB L1 cache from the 64 KB L1 cache configuration is optional. To offset this smaller L1 memory, the branch predictor is better at covering irregular search patterns and is capable of following two taken branches per cycle, which results in fewer L1 cache misses and helps hide pipeline bubbles to keep the core well supplied. The pipeline is one cycle longer compared to the A77, which ensures that the A78 hits a clock frequency target of around 3 GHz. The A78 is a 6 instruction per cycle design.

ARM also introduced a second integer multiple unit in the execution unit and an additional load Address Generation Unit (AGU) to increase both the data load and bandwidth by 50%. Other optimizations of the chipset include fused instructions and efficiency improvements to instruction schedulers, register renaming structures, and the reorder buffer.

L2 cache is variable up to 512 KB and has double the bandwidth to maximize the performance, while the shared L3 cache is variable up to 4 MB, double that of previous generations. A Dynamic Shared Unit (DSU) also allows for an 8 MB configuration with the ARM Cortex-X1.[2][3][4][5]

Licensing

The Cortex-A78 is available as a SIP core to licensees whilst its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).

Usage

See also

• ARM Cortex-X1
• ARM Cortex-A76
• ARM Cortex-A75
• Exynos
• Qualcomm Snapdragon

References

1. "Cortex-A78". Arm Developer. Retrieved 2020-07-01.
2. Frumusanu, Andrei. "Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence". www.anandtech.com. Retrieved 2020-06-17.
3. "Arm Unveils the Cortex-A78: When Less Is More". WikiChip Fuse. 2020-05-26. Retrieved 2020-06-17.
4. Triggs, Robert (2020-05-26). "Arm Cortex-X1 and Cortex-A78 CPUs: Big cores with big differences". Android Authority. Retrieved 2020-06-15.
5. "ARM's Cortex-A78 CPU and Mali-G78 GPU will power 2021's best Android phones". www.theverge.com. Retrieved 2020-06-15.

External links