Comparison of instruction set architectures

An instruction set architecture (ISA) is an abstract model of a computer. It is also referred to as architecture or computer architecture. A realization of an ISA is called an implementation. An ISA permits multiple implementations that may vary in performance, physical size, and monetary cost (among other things); because the ISA serves as the interface between software and hardware. Software that has been written for an ISA can run on different implementations of the same ISA. This has enabled binary compatibility between different generations of computers to be easily achieved, and the development of computer families. Both of these developments have helped to lower the cost of computers and to increase their applicability. For these reasons, the ISA is one of the most important abstractions in computing today.

An ISA defines everything a machine language programmer needs to know in order to program a computer. What an ISA defines differs between ISAs; in general, ISAs define the supported data types, what state there is (such as the main memory and registers) and their semantics (such as the memory consistency and addressing modes), the instruction set (the set of machine instructions that comprises a computer's machine language), and the input/output model.

Base

In the early decades of computing, there were computers that used binary, decimal[1] and even ternary.[2][3] Contemporary computers are almost exclusively binary.

Bits

Computer architectures are often described as n-bit architectures. Today n is often 8, 16, 32, or 64, but other sizes have been used (including 6, 12, 18, 24, 30, 36, 39, 48, 60). This is actually a strong simplification. A computer architecture often has a few more or less "natural" datasizes in the instruction set, but the hardware implementation of these may be very different. Many instruction set architectures have instructions that, on some implementations of that instruction set architecture, operate on half and/or twice the size of the processor's major internal datapaths. Examples of this are the 8080, Z80, MC68000 as well as many others. On these types of implementations, a twice as wide operation typically also takes around twice as many clock cycles (which is not the case on high performance implementations). On the 68000, for instance, this means 8 instead of 4 clock ticks, and this particular chip may be described as a 32-bit architecture with a 16-bit implementation. The IBM System/360 instruction set architecture is 32-bit, but several models of the System/360 series, such as the IBM System/360 Model 30, have 8-bit internal data paths. The external databus width is often not useful to determine the width of the architecture; the NS32008, NS32016 and NS32032 were basically the same 32-bit chip with different external data buses. The NS32764 had a 64-bit bus, but used 32-bit registers.

The width of addresses may or may not be different from the width of data. Early 32-bit microprocessors often had a 24-bit address, as did the System/360 processors.

Operands

The number of operands is one of the factors that may give an indication about the performance of the instruction set. A three-operand architecture will allow

A := B + C

to be computed in one instruction.

A two-operand architecture will allow

A := A + B

to be computed in one instruction, so two instructions will need to be executed to simulate a single three-operand instruction

A := B
A := A + C

Endianness

An architecture may use "big" or "little" endianness, or both, or be configurable to use either. Little endian processors order bytes in memory with the least significant byte of a multi-byte value in the lowest-numbered memory location. Big endian architectures instead order them with the most significant byte at the lowest-numbered address. The x86 architecture as well as several 8-bit architectures are little endian. Most RISC architectures (SPARC, Power, PowerPC, MIPS) were originally big endian (ARM was little endian), but many (including ARM) are now configurable.

Endianness only applies to processors that allow individual addressing of units of data (such as bytes) that are smaller than the basic addressable machine word.

Instruction sets

Usually the number of registers is a power of two, e.g. 8, 16, 32. In some cases a hardwired-to-zero pseudo-register is included, as "part" of register files of architectures, mostly to simplify indexing modes. This table only counts the integer "registers" usable by general instructions at any moment. Architectures always include special-purpose registers such as the program pointer (PC). Those are not counted unless mentioned. Note that some architectures, such as SPARC, have register window; for those architectures, the count below indicates how many registers are available within a register window. Also, non-architected registers for register renaming are not counted.

Note, a common type of architecture, "load-store", is a synonym for "Register Register" below, meaning no instructions access memory except special – load to register(s) – and store from register(s) – with the possible exceptions of atomic memory operations for locking.

The table below compares basic information about instruction sets to be implemented in the CPU architectures:

Archi- tecture	Bits	Version	Intro- duced	Max # operands	Type	Design	Registers (excluding FP/vector)	Instruction encoding	Branch evaluation	Endian- ness	Extensions	Open	Royalty free
6502	8		1975	1	Register Memory	CISC	3	Variable (8- to 32-bit)	Condition register	Little
6809	8		1978	1	Register Memory	CISC	9	Variable (8- to 32-bit)	Condition register	Big
680x0	32		1979	2	Register Memory	CISC	8 data and 8 address	Variable	Condition register	Big
8080	8		1974	2	Register Memory	CISC	8	Variable (8 to 24 bits)	Condition register	Little
8051	32 (8→32)		1977?	1	Register Register	CISC	32 in 4-bit 16 in 8-bit 8 in 16-bit 4 in 32-bit	Variable (8-bit to 128 bytes)	Compare and branch	Little
x86	16, 32, 64 (16→32→64)		1978	2 (integer) 3 (AVX)[4] 4 (FMA4)[5]	Register Memory	CISC	8 (+ 4 or 6 segment reg.) (16/32-bit) 16 (+ 2 segment reg. gs/cs) (64-bit)	Variable (8086 ~ 80386: variable between 1 and 6 bytes /w MMU + intel SDK, 80486: 2 to 5 bytes with prefix, pentium and onward: 2 to 4 bytes with prefix, x64: 4 bytes prefix, third party x86 emulation: 1 to 15 bytes w/o prefix & MMU . SSE/MMX: 4 bytes /w prefix AVX: 8 Bytes /w prefix)	Condition code	Little	x87, IA-32, MMX, 3DNow!, SSE, SSE2, PAE, x86-64, SSE3, SSSE3, SSE4, BMI, AVX, AES, FMA, XOP, F16C	No	No
Alpha	64		1992	3	Register Register	RISC	32 (including "zero")	Fixed (32-bit)	Condition register	Bi	MVI, BWX, FIX, CIX	No
ARC	16/32	ARCv2[6]	1996	3	Register Register	RISC	16 or 32 including SP user can increase to 60	Variable (16- and 32-bit)	Compare and branch	Bi	APEX User-defined instructions
ARM/A32	32	ARMv1-v8	1983	3	Register Register	RISC	15	Fixed (32-bit)	Condition code	Bi	NEON, Jazelle, VFP, TrustZone, LPAE		No
Thumb/T32	32	ARMv4T-ARMv8	1994	3	Register Register	RISC	7 with 16-bit Thumb instructions 15 with 32-bit Thumb-2 instructions	Thumb: Fixed (16-bit), Thumb-2: Variable (16- and 32-bit)	Condition code	Bi	NEON, Jazelle, VFP, TrustZone, LPAE		No
Arm64/A64	64	ARMv8-A[7]	2011[8]	3	Register Register	RISC	32 (including the stack pointer/"zero" register)	Fixed (32-bit)	Condition code	Bi	none: all ARMv7 extensions are non-optional		No
AVR	8		1997	2	Register Register	RISC	32 16 on "reduced architecture"	Variable (mostly 16-bit, four instructions are 32-bit)	Condition register, skip conditioned on an I/O or general purpose register bit, compare and skip	Little
AVR32	32	Rev 2	2006	2–3		RISC	15	Variable[9]		Big	Java Virtual Machine
Blackfin	32		2000	3[10]	Register Register	RISC[11]	2 accumulators 8 data registers 8 pointer registers 4 index registers 4 buffer registers	Variable(16- or 32-bit)	Condition code	Little[12]
CDC 6000	60		1964	3	Register Memory	RISC	24 (8 18-bit address reg., 8 18-bit index reg., 8 60-bit operand reg.)	Variable (15, 30, and 60-bit)	Compare and branch	n/a[13]	Compare/Move Unit, additional Peripheral Processing Units	No	No
Crusoe (native VLIW)	32[14]		2000	1	Register Register[14]	VLIW[14][15]	1 in native push stack mode 6 in x86 emulation + 8 in x87/MMX mode + 50 in rename status 12 integer + 48 shadow + 4 debug in native VLIW mode[14][15]	Variable (64- or 128-bit in native mode, 15 bytes in x86 emulation)[15]	Condition code[14]	Little
Elbrus (native VLIW)	64	Elbrus-4S	2014	1	Register Register[14]	VLIW	8–64	64	Condition code	Little	Just-in-time dynamic trans- lation: x87, IA-32, MMX, SSE, SSE2, x86-64, SSE3, AVX	No	No
DLX	32		1990	3		RISC	32	Fixed (32-bit)		Big
eSi-RISC	16/32		2009	3	Register Register	RISC	8–72	Variable (16- or 32-bit)	Compare and branch and condition register	Bi	User-defined instructions	No	No
Itanium (IA-64)	64		2001		Register Register	EPIC	128	Fixed (128 bit bundles with 5 bit template tag and 3 instructions, each 41 bit long)	Condition register	Bi (selectable)	Intel Virtualization Technology	No	No
M32R	32		1997	3	Register Register	RISC	16	Variable (16- or 32-bit)	Condition register	Bi
Mico32	32	?	2006	3	Register Register	RISC	32[16]	Fixed (32-bit)	Compare and branch	Big	User-defined instructions	Yes[17]	Yes
MIPS	64 (32→64)	6[18][19]	1981	1–3	Register Register	RISC	4–32 (including "zero")	Fixed (32-bit)	Condition register	Bi	MDMX, MIPS-3D	No	No[20][21]
MMIX	64	?	1999	3	Register Register	RISC	256	Fixed (32-bit)	?	Big	?	Yes	Yes
NS320xx	32		1982	5	Memory Memory	CISC	8	Variable Huffman coded, up to 23 bytes long	Condition code	Little	BitBlt instructions
OpenRISC	32, 64	1.3[22]	2010	3	Register Register	RISC	16 or 32	Fixed	?	?	?	Yes	Yes
PA-RISC (HP/PA)	64 (32→64)	2.0	1986	3	Register Register	RISC	32	Fixed (32-bit)	Compare and branch	Big → Bi	MAX	No
PDP-8[23]	12		1966		Register Memory	CISC	1 accumulator 1 multiplier quotient register	Fixed (12-bit)	Condition register Test and branch		EAE(Extended Arithmetic Element)
PDP-11	16		1970	3	Memory Memory	CISC	8 (includes stack pointer, though any register can act as stack pointer)	Fixed (16-bit)	Condition code	Little	Floating Point, Commercial Instruction Set	No	No
POWER, PowerPC, Power ISA	32/64 (32→64)	3.0B[24]	1990	3	Register Register	RISC	32	Fixed (32-bit), Variable	Condition code	Big/Bi	AltiVec, APU, VSX, Cell	Yes	Yes
RISC-V	32, 64, 128	2.2[25]	2010	3	Register Register	RISC	32 (including "zero")	Variable	Compare and branch	Little	?	Yes	Yes
RX	64/32/16		2000	3	Memory Memory	CISC	4 integer + 4 address	Variable	Compare and branch	Little			No
S+core	16/32		2005			RISC				Little
SPARC	64 (32→64)	OSA2017[26]	1985	3	Register Register	RISC	32 (including "zero")	Fixed (32-bit)	Condition code	Big → Bi	VIS	Yes	Yes[27]
SuperH (SH)	32		1994	2	Register Register Register Memory	RISC	16	Fixed (16- or 32-bit), Variable	Condition code (single bit)	Bi
System/360 System/370 z/Architecture	64 (32→64)		1964	2 (most) 3 (FMA, distinct operand facility) 4 (some vector inst.)	Register Memory Memory Memory Register Register	CISC	16	Variable (16-, 32-, or 48-bit)	Condition code, compare and branch	Big		No	No
Transputer	32 (4→64)		1987	1	Stack machine	MISC	3 (as stack)	Variable (8 ~ 120 bytes)	Compare and branch	Little
VAX	32		1977	6	Memory Memory	CISC	16	Variable	Compare and branch	Little
Z80	8		1976	2	Register Memory	CISC	17	Variable (8 to 32 bits)	Condition register	Little
Archi- tecture	Bits	Version	Intro- duced	Max # operands	Type	Design	Registers (excluding FP/vector)	Instruction encoding	Branch evaluation	Endian- ness	Extensions	Open	Royalty free

See also

• Central processing unit (CPU)
• CPU design
• Comparison of CPU microarchitectures
• Instruction set
• Microprocessor
• Benchmark (computing)

References

1. da Cruz, Frank (October 18, 2004). "The IBM Naval Ordnance Research Calculator". Columbia University Computing History. Retrieved January 28, 2019.
2. "Russian Virtual Computer Museum – Hall of Fame – Nikolay Petrovich Brusentsov".
3. Trogemann, Georg; Nitussov, Alexander Y.; Ernst, Wolfgang (2001). Computing in Russia: the history of computer devices and information technology revealed. Vieweg+Teubner Verlag. pp. 19, 55, 57, 91, 104–107. ISBN 978-3-528-05757-2..
4. The LEA (8086 & later) and IMUL-immediate (80186 & later) instructions accept three operands; most other instructions of the base integer ISA accept no more than two operands.
5. https://www.amd.com/system/files/TechDocs/43479.pdf
6. https://www.synopsys.com/designware-ip/processor-solutions/arc-processors.html
7. "ARMv8 Technology Preview" (PDF). Archived from the original (PDF) on 2018-06-10. Retrieved 2011-10-28.
8. "ARM goes 64-bit with new ARMv8 chip architecture". Retrieved 26 May 2012.
9. "AVR32 Architecture Document" (PDF). Atmel. Retrieved 2008-06-15.
10. "Blackfin manual" (PDF). analog.com.
11. "Blackfin Processor Architecture Overview". Analog Devices. Retrieved 2009-05-10.
12. "Blackfin memory architecture". Analog Devices. Archived from the original on 2011-06-16. Retrieved 2009-12-18.
13. Since memory is an array of 60-bit words with no means to access sub-units, big endian vs. little endian makes no sense. The optional CMU unit uses big endian semantics.
14. "Crusoe Exposed: Transmeta TM5xxx Architecture 2". Real World Technologies.
15. Alexander Klaiber (January 2000). "The Technology Behind Crusoe Processors" (PDF). Transmeta Corporation. Retrieved December 6, 2013.
16. "LatticeMico32 Architecture". Lattice Semiconductor. Archived from the original on 23 June 2010.
17. "LatticeMico32 Open Source Licensing". Lattice Semiconductor. Archived from the original on 20 June 2010.
18. MIPS64 Architecture for Programmers: Release 6
19. MIPS32 Architecture for Programmers: Release 6
20. MIPS Open
22. OpenRISC Architecture Revisions
23. "PDP-8 Users Handbook" (PDF). bitsavers.org. 2019-02-16.
24. "Power ISA Version 3.0". openpowerfoundation.org. 2016-11-30. Retrieved 2017-01-06.
25. "RISC-V ISA Specifications". Retrieved 17 June 2019.
26. Oracle SPARC Processor Documentation
27. SPARC Architecture License