Epyc

Epyc is a brand of x86-64 microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Introduced in June 2017, they are specifically targeted for the server and embedded system markets.[1] Epyc processors share the same microarchitecture as their regular desktop-grade counterparts, but have enterprise-grade features such as higher core counts, more PCI Express lanes, support for larger amounts of RAM, and larger cache memory. They also support multi-chip and dual-socket system configurations by using Infinity Fabric interchip interconnect.

AMD Epyc

General Info
Launched	June 2017
Marketed by	AMD
Designed by	AMD
Common manufacturer(s)	GlobalFoundries (14 nm) TSMC (7 nm)
Performance
Max. CPU clock rate	2.7 GHz to 3.9 GHz
Architecture and classification
Min. feature size	14 nm to 7 nm
Microarchitecture	Zen Zen 2
Instruction set	AMD64/x86-64, MMX(+), SSE1, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AES, CLMUL, AVX, AVX2, FMA3, CVT16/F16C, ABM, BMI1, BMI2, SHA
Physical specifications
Cores	up to 128 cores/256 threads on dual-socket systems
Socket(s)	SP3
Products, models, variants
Core name(s)	Naples Rome
Brand name(s)	Epyc
History
Predecessor	Opteron

History

In March 2017, AMD announced a server platform based on the Zen microarchitecture, codenamed Naples, and officially revealed it under the brand name Epyc in May.[2] That June, AMD officially launched Epyc by releasing the Epyc 7001 series processors.[3] Two years later, in August 2019, the Epyc 7002 series processors based on the Zen 2 microarchitecture released, bringing much better performance and double the cores compared to their predecessors.

The future Zen 3 based Epyc microarchitecture will be codenamed "Milan".[4]

AMD EPYC CPU Codenames[5]

Gen	Year	Name	Cores
1st	2017	Naples	32 x Zen 1
2nd	2019	Rome	64 x Zen 2
3rd	2020	Milan	64 x Zen 3
4th	2022	Genoa	? x Zen 4
5th	?	?	? x Zen 5

Design

The platform includes one- and two-socket systems. In multi-processor configurations, two Epyc CPUs communicate via AMD's Infinity Fabric.[6] Each server chip supports 8 channels of memory and 128 PCIe 3.0 lanes, of which 64 lanes from each are used for CPU-to-CPU communication through Infinity Fabric when installed in a dual-processor configuration.[7] All Epyc processors are composed of four eight-core Zeppelin dies (the same die as found in Ryzen processors) in a multi-chip module, with the varying product core counts produced by symmetrically disabling cores of each core complex on each Zeppelin die.[8][9]

Unlike Opteron, Intel equivalents and AMD's desktop processors (excluding Socket AM1), Epyc processors are chipset-free - also known as system on a chip. That means most features required to make servers fully functional (such as memory, PCI Express, SATA controllers etc.) are fully integrated into the processor, eliminating the need for a chipset to be placed on the mainboard. Some unavailable features require additional controller chips to make them available on the system.

The first generation of Epyc microprocessors were manufactured by GlobalFoundries using a 14 nm FinFET process licensed from Samsung Electronics.[10] Epyc 2 will be manufactured by TSMC using a 7 nm FinFET process.[11]

Reception

Initial reception to Epyc was generally positive.[12] Epyc was generally found to outperform Intel CPUs in cases where the cores could work independently, such as in high-performance computing and big-data applications. First generation Epyc fell behind in database tasks compared to Intel's Xeon parts due to higher cache latency.[12]

Features

CPU features table

Products

Server

First generation Epyc (Naples)

The following table lists the devices using the first generation design.

A "P" suffix denotes support for only a single socket configuration. Non-P models use 64 PCI-E lanes from each processor for the communication between processors.

Model	Fab	Socket configu- ration	Cores/FPUs (threads)	Clock rate (GHz)			Cache[lower-alpha 1]			PCIe Lanes	Memory support	TDP	Release date	Release price (USD)
				Base	Boost		L1 (KB)	L2 (KB)	L3 (MB)
					All-core	Max
EPYC 7351P[14] [15][16]	14nm	1P	16 (32)	2.4	2.9		64 KB inst. 32 KB data per core	512 KB per core	64	128	DDR4-2666 8 channels	155/170 W	June 2017 [17]	0 $750+
EPYC 7401P[14] [15][16]			24 (48)	2.0	2.8	3.0								$1075+
EPYC 7551P[14][15][16]			32 (64)		2.55							180 W		$2100+
EPYC 7251[14][15][16]		2P	8 (16)	2.1	2.9				32		DDR4-2400 8 channels	120 W		0 $475+
EPYC 7261[18]				2.5					64		DDR4-2666 8 channels	155/170 W	Mid 2018	0$700+
EPYC 7281[14][15][16]			16 (32)	2.1	2.7				32				June 2017 [17]	0 $650+
EPYC 7301[14][15][16]				2.2					64					0$800+
EPYC 7351[14][15][16]				2.4	2.9									$1100+
EPYC 7371[19]				3.1	3.6	3.8						180 W	Late 2018	$1550+
EPYC 7401[14][15][16]			24 (48)	2.0	2.8	3.0						155/170 W	June 2017 [17]	$1850+
EPYC 7451[14][15][16]				2.3	2.9	3.2						180 W		$2400+
EPYC 7501[14][15][16]			32 (64)	2.0	2.6	3.0						155/170 W		$3400+
EPYC 7551[14][15][16]					2.55							180 W		$3400+
EPYC 7601[14][15][16]				2.2	2.7	3.2								$4200+

1. AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[13]

Second generation Epyc (Rome)

First generation Epyc processor

In November 2018 AMD announced Epyc 2 at their Next Horizon event, the second generation of Epyc processors code-named "Rome" and based on the Zen 2 microarchitecture.[20] The processors feature up to eight 7 nm-based "chiplet" processors with a 14 nm-based IO chip in the center interconnected via Infinity Fabric. The processors support up to 8 channels of DDR4 RAM up to 4 TB, and introduce support for PCIe 4.0. These processors have up to 64 cores with 128 SMT threads per socket.[21] The 7 nm "Rome" is manufactured by TSMC.[11] It was released on August 7, 2019.[22]

Common features of these CPUs:

• Codenamed "Rome"
• The number of PCI-E lanes: 128
• Socket: SP3
• Release date: August 7, 2019 except EPYC 7H12 which was released on September 18, 2019
• Memory support: eight-channel DDR4-3200

Model	Fab	Socket configu- ration	Cores/FPUs (threads)	Clock rate (GHz)			Cache[lower-alpha 1]			TDP	Release price (USD)
				Base	Boost		L1 (KB)	L2 (KB)	L3 (MB)
					All-core	Max
EPYC 7232P	7nm	1P	8 (16)	3.1		3.2	32 KB inst. 32 KB data per core	512 KB per core	32	120 W	$450
EPYC 7302P			16 (32)	3		3.3			128	155 W	$825
EPYC 7402P			24 (48)	2.8		3.35				180 W	$1250
EPYC 7502P			32 (64)	2.5		3.35					$2300
EPYC 7702P			64 (128)	2		3.35			256	200 W	$4425
EPYC 7252		2P	8 (16)	3.1		3.2			64	120 W	$475
EPYC 7262				3.2		3.4			128	155 W	$575
EPYC 7272			12 (24)	2.9		3.2			64	120 W	$625
EPYC 7282			16 (32)	2.8		3.2					$650
EPYC 7302				3		3.3			128	155 W	$978
EPYC 7352			24 (48)	2.3		3.2					$1350
EPYC 7402				2.8		3.35				180 W	$1783
EPYC 7452			32 (64)	2.35		3.35				155 W	$2025
EPYC 7502				2.5		3.35				180 W	$2600
EPYC 7532				2.4		3.3			256	200 W	$3350
EPYC 7542				2.9		3.4			128	225 W	$3400
EPYC 7552			48 (96)	2.2		3.3			192	200 W	$4025
EPYC 7642				2.3		3.3			256	225 W	$4775
EPYC 7662			64 (128)	2		3.3				225 W	$6150
EPYC 7702				2		3.35				200 W	$6450
EPYC 7742				2.25		3.4				225 W	$6950
EPYC 7H12				2.6		3.3				280 W
EPYC 7F32		1P/2P	8 (16)	3.7		3.9			128	180 W	$2100
EPYC 7F52			16 (32)	3.5		3.9			256	240 W	$3100
EPYC 7F72			24 (48)	3.2		3.7			192	240 W	$2450

1. AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[13]

Third generation Epyc (Milan)

At the HPC-AI Advisory Council in the United Kingdom in October 2019, AMD stated specifications for Milan, Epyc chips based on the Zen 3 microarchitecture.[23] Milan chips will use Socket SP3, with up to 64 cores on die, and support eight DDR4 SDRAM and PCIe 4.0 channels.[23] It also announced plans for the subsequent generation of chips, codenamed Genoa, that will be based on the Zen 4 microarchitecture and use Socket SP5.[23]

Embedded

First generation Epyc (Snowy Owl)

In February 2018, AMD also announced the EPYC 3000 series of embedded Zen CPUs.[24]

Model	Release date	Fab	Socket	Cores/FPUs (threads)	Clock rate (GHz)			Cache[lower-roman 1]			Memory support	Ethernet	TDP	Junction temperature (°C)
					Base	Boost		L1	L2	L3
						All-core	Max
EPYC 3101	February 2018	14nm	SP4r2	4 (4)	2.1	2.9	2.9	64 KB inst. 32 KB data per core	512 KB per core	8 MB	DDR4-2666 dual-channel	4 × 10GbE	35 W	0-95
EPYC 3151				4 (8)	2.7	2.9	2.9			16 MB			45 W
EPYC 3201				8 (8)	1.5	3.1	3.1			16 MB	DDR4-2133 dual-channel		30 W
EPYC 3251				8 (16)	2.5	3.1	3.1				DDR4-2666 dual-channel		55 W	0-105
EPYC 3255	Unknown												25-55 W	-40-105
EPYC 3301	February 2018			12 (12)	2.0	2.15	3.0			32 MB	DDR4-2666 quad-channel	8 × 10GbE	65 W	0-95
EPYC 3351			SP4	12 (24)	1.9	2.75	3.0						60-80 W	0-105
EPYC 3401			SP4r2	16 (16)	1.85	2.25	3.0			32 MB			85 W
EPYC 3451			SP4	16 (32)	2.15	2.45	3.0						80-100 W

1. AMD defines 1 kilobyte (KB) as 1024 bytes, and 1 megabyte (MB) as 1024 kilobytes.[13]

Chinese variants

A variant created for the Chinese server market by an AMD–Chinese joint venture is the Hygon Dhyana system on a chip.[25][26] It is noted to be a variant of the AMD EPYC, and is so similar that "there is little to no differentiation between the chips".[25] It has been noted that there is "less than 200 lines of new kernel code" for Linux kernel support, and that the Dhyana is "mostly a re-branded Zen CPU for the Chinese server market".[26] Later Benchmarks showed that certain floating point instructions are performing worse and AES is disabled, probably to comply with US export restrictions.[27]

References

1. Cutress, Ian. "Computex 2017: AMD Press Event Live Blog". www.anandtech.com.
2. Kampman, Jeff (16 May 2017). "AMD's Naples datacenter CPUs will make an Epyc splash". Tech Report. Retrieved 16 May 2017.
3. Cutress, Ian (20 June 2017). "AMD's Future in Servers: New 7000-Series CPUs Launched and EPYC Analysis". Anandtech. Retrieved 12 July 2017.
4. https://www.anandtech.com/show/14568/an-interview-with-amds-forrest-norrod-naples-rome-milan-genoa
5. AMD Confirms Zen 4 EPYC Codename, and Elaborates on Frontier Supercomputer CPU. AnandTech.
6. Kampman, Jeff (7 March 2017). "AMD's Naples platform prepares to take Zen into the datacenter". Tech Report. Retrieved 7 March 2017.
7. Cutress, Ian (7 March 2017). "AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2". Anandtech. Retrieved 7 March 2017.
8. Shrout, Ryan (20 June 2017). "AMD EPYC 7000 Series Data Center Processor Launch – Gunning for Xeon | Architectural Outlook". www.pcper.com. Retrieved 9 August 2019.
9. Morgan, Timothy Prickett (May 17, 2017). "AMD Disrupts The Two-Socket Server Status Quo". www.nextplatform.com.
10. Morris, John (March 13, 2018). "Inside GlobalFoundries' long road to the leading edge". ZDNet. Retrieved 17 July 2019.
11. Smith, Ryan (July 26, 2018). "AMD "Rome" EPYC CPUs to Be Fabbed By TSMC". AnandTech. Retrieved 18 June 2019.
12. De Gelas, Johan; Cutress, Ian (11 July 2017). "Sizing Up the Servers: Intel's Skylake-SP Xeon vs AMD's EPYC 7000". Anandtech. Retrieved 11 July 2017.
13. "Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors" (PDF). AMD Technical Documentation. AMD Developer Central: Advanced Micro Devices, Inc. 2017-04-15. p. 25. Retrieved 2019-11-01.
14. "AMD EPYC™ 7000 Series Processors: Leading Performance for the Cloud Era" (PDF). Advanced Micro Devices, Inc. August 2018. p. 2.
15. Cutress, Ian (20 June 2017). "AMD's Future in Servers: New 7000-Series CPUs Launched and EPYC Analysis". Anand Tech. Retrieved 21 June 2017.
16. Cutress, Ian (20 June 2017). "AMD EPYC Launch Event Live Blog". Anand Tech. Retrieved 21 June 2017.
17. Kennedy, Patrick (16 May 2017). "AMD EPYC New Details on the Emerging Server Platform". Serve The Home. Retrieved 16 May 2017.
18. "AMD EPYC™ 7261 | AMD". www.amd.com. Retrieved 2019-01-20.
19. "AMD PS7371BEVGPAF EPYC 7371 3.1GHz 16-Core". www.gamepc.com. Retrieved 2019-01-20.
20. "AMD Takes High-Performance Datacenter Computing to the Next Horizon". AMD. Retrieved 2018-12-06.
21. Gordon Mah Ung (2018-11-07). "What AMD's 64-core 'Rome' server CPU tells us about Ryzen 2". PCWorld. Retrieved 2018-11-08.
22. "2nd Gen AMD EPYC™ Processors Set New Standard for the Modern Datacenter with Record-Breaking Performance and Significant TCO Savings". AMD. August 7, 2019. Retrieved August 8, 2019.
23. Alcorn, Paul (5 October 2019). "AMD dishes on Zen 3 and Zen 4 architecture, Milan and Genoa roadmap". Tom's Hardware. Retrieved 5 October 2019.
24. Alcorn, Paul (21 February 2018). "AMD Launches Ryzen Embedded V1000, EPYC Embedded 3000 Processors". tom's HARDWARE. Retrieved 5 April 2018.
25. Alcorn, Paul (6 July 2018). "China Finds Zen: Begins Production Of x86 Processors Based On AMD's IP". Tom's Hardware. Retrieved 9 July 2018.
26. Larabel, Michael (9 June 2018). "Hygon Dhyana: Chinese x86 Server CPUs Based On AMD Zen". Phoronix. Retrieved 9 July 2018.
27. Cutress, Ian. "Testing a Chinese x86 CPU: A Deep Dive into Zen-based Hygon Dhyana Processors". www.anandtech.com.