Socket FP3
The Socket FP3 or µBGA906 is a CPU socket for laptops that was released in June 2014 by AMD with its mobility APU products codenamed Kaveri.
Type | µBGA |
---|---|
Chip form factors | ? |
Contacts | 906 |
Processors | mobile APU products (Kaveri) |
This article is part of the CPU socket series |
"Kaveri"-branded ULV products combine Steamroller with Crystal Series (GCN), UVD 4.2 and VCE 2 video acceleration, AMD TrueAudio audio acceleration and AMD Eyefinity-based multi-monitor support of up to two non-DisplayPort- or up to four DisplayPort monitors.
- ECC DIMMs are supported on Socket FP3, mixing of ECC and non-ECC DIMMs within a system is not supported.[1]
- There are 3 PCI Express cores: one 2 x16 core and two 5 x8 cores, for a total of 64 lanes. There are 8 configurable ports, which can be divided into 2 groups:
- Gfx-group: contains 2 x8 ports. Each port can be limited to lower link widths for applications that require fewer lanes. Additionally, the two ports can be combined to create a single x16 link.
- GPP-group: contains 1 x4 UMI and 5 General Purpose Ports (GPP).
All PCIe links are capable of supporting PCIe 2.x data rates. In addition, the Gfx link is capable of supporting PCIe 3.x data rate. The FP3 package supports two different voltage levels on the VDDP rail. At the 1.05 V nominal setting, the Gfx link can support PCI Express 3.x data rate, while at the 0.95 V setting, the maximum data rate supported by the Gfx link is PCI Express 2.x[1]
- The FP3 package supports two different voltage levels on the VDDR rail. At the 1.05 V nominal setting, the maximum speed of DDR3-2133 can be supported while at the 0.95 V setting, the maximum speed supported is DDR3-1600..[1]
Its desktop counterpart is Socket FM2+.
Feature overview
The following table shows features of AMD's APUs (see also: List of AMD accelerated processing units).
Codename | Server | Basic | Toronto | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Micro | Kyoto | |||||||||||||||||
Desktop | Mainstream | Carrizo | Bristol Ridge | Raven Ridge | Picasso | Renoir | ||||||||||||
Entry | Llano | Trinity | Richland | Kaveri | ||||||||||||||
Basic | Kabini | |||||||||||||||||
Mobile | Performance | Renoir | ||||||||||||||||
Mainstream | Llano | Trinity | Richland | Kaveri | Carrizo | Bristol Ridge | Raven Ridge | Picasso | ||||||||||
Entry | Dalí | |||||||||||||||||
Basic | Desna, Ontario, Zacate | Kabini, Temash | Beema, Mullins | Carrizo-L | Stoney Ridge | |||||||||||||
Embedded | Trinity | Bald Eagle | Merlin Falcon, Brown Falcon |
Great Horned Owl | Ontario, Zacate | Kabini | Steppe Eagle, Crowned Eagle, LX-Family |
Prairie Falcon | Banded Kestrel | |||||||||
Platform | High, standard and low power | Low and ultra-low power | ||||||||||||||||
Released | Aug 2011 | Oct 2012 | Jun 2013 | Jan 2014 | Jun 2015 | Jun 2016 | Oct 2017 | Jan 2019 | Mar 2020 | Jan 2011 | May 2013 | Apr 2014 | May 2015 | Feb 2016 | Apr 2019 | |||
CPU microarchitecture | K10 | Piledriver | Steamroller | Excavator | "Excavator+"[2] | Zen | Zen+ | Zen 2 | Bobcat | Jaguar | Puma | Puma+[3] | "Excavator+" | Zen | ||||
ISA | x86-64 | x86-64 | ||||||||||||||||
Socket | Desktop | High-end | N/A | N/A | ||||||||||||||
Mainstream | N/A | AM4 | ||||||||||||||||
Entry | FM1 | FM2 | FM2+[lower-alpha 1] | N/A | ||||||||||||||
Basic | N/A | N/A | AM1 | N/A | ||||||||||||||
Other | FS1 | FS1+, FP2 | FP3 | FP4 | FP5 | FP6 | FT1 | FT3 | FT3b | FP4 | FP5 | |||||||
PCI Express version | 2.0 | 3.0 | 4.0 | 2.0 | 3.0 | |||||||||||||
Fab. (nm) | GF 32SHP (HKMG SOI) |
GF 28SHP (HKMG bulk) |
GF 14LPP (FinFET bulk) |
GF 12LP (FinFET bulk) |
TSMC N7 (FinFET bulk) |
TSMC N40 (bulk) |
TSMC N28 (HKMG bulk) |
GF 28SHP (HKMG bulk) |
GF 14LPP (FinFET bulk) | |||||||||
Die area (mm2) | 228 | 246 | 245 | 245 | 250 | 210[4] | 156 | 75 (+ 28 FCH) | 107 | ? | 125 | 149 | ||||||
Min TDP (W) | 35 | 17 | 12 | 10 | 4.5 | 4 | 3.95 | 10 | 6 | |||||||||
Max APU TDP (W) | 100 | 95 | 65 | 18 | 25 | |||||||||||||
Max stock APU base clock (GHz) | 3 | 3.8 | 4.1 | 3.7 | 3.8 | 3.6 | 3.7 | 3.8 | 1.75 | 2.2 | 2 | 2.2 | 3.2 | 3.3 | ||||
Max APUs per node[lower-alpha 2] | 1 | 1 | ||||||||||||||||
Max CPU[lower-alpha 3] cores per APU | 4 | 8 | 2 | 4 | 2 | |||||||||||||
Max threads per CPU core | 1 | 2 | 1 | 2 | ||||||||||||||
Integer structure | 3+3 | 2+2 | 4+2 | 4+2+1 | 1+1+1+1 | 2+2 | 4+2 | |||||||||||
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF | ![]() | ![]() | ||||||||||||||||
IOMMU[lower-alpha 4] | N/A | ![]() | ||||||||||||||||
BMI1, AES-NI, CLMUL, and F16C | N/A | ![]() | ||||||||||||||||
MOVBE | N/A | ![]() | ||||||||||||||||
AVIC, BMI2 and RDRAND | N/A | ![]() | ||||||||||||||||
ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, and CLZERO | N/A | ![]() | N/A | ![]() | ||||||||||||||
WBNOINVD, CLWB, RDPID, RDPRU, and MCOMMIT | N/A | ![]() | N/A | |||||||||||||||
FPUs per core | 1 | 0.5 | 1 | 1 | 0.5 | 1 | ||||||||||||
Pipes per FPU | 2 | 2 | ||||||||||||||||
FPU pipe width | 128-bit | 256-bit | 80-bit | 128-bit | ||||||||||||||
CPU instruction set SIMD level | SSE4a[lower-alpha 5] | AVX | AVX2 | SSSE3 | AVX | AVX2 | ||||||||||||
3DNow! | 3DNow!+ | N/A | N/A | |||||||||||||||
PREFETCH/PREFETCHW | ![]() | ![]() | ||||||||||||||||
FMA4, LWP, TBM, and XOP | N/A | ![]() | N/A | N/A | ![]() | N/A | ||||||||||||
FMA3 | ![]() | ![]() | ||||||||||||||||
L1 data cache per core (KiB) | 64 | 16 | 32 | 32 | ||||||||||||||
L1 data cache associativity (ways) | 2 | 4 | 8 | 8 | ||||||||||||||
L1 instruction caches per core | 1 | 0.5 | 1 | 1 | 0.5 | 1 | ||||||||||||
Max APU total L1 instruction cache (KiB) | 256 | 128 | 192 | 256 | 512 | 64 | 128 | 96 | 128 | |||||||||
L1 instruction cache associativity (ways) | 2 | 3 | 4 | 8 | 2 | 3 | 4 | |||||||||||
L2 caches per core | 1 | 0.5 | 1 | 1 | 0.5 | 1 | ||||||||||||
Max APU total L2 cache (MiB) | 4 | 2 | 4 | 1 | 2 | 1 | ||||||||||||
L2 cache associativity (ways) | 16 | 8 | 16 | 8 | ||||||||||||||
APU total L3 cache (MiB) | N/A | 4 | 8 | N/A | 4 | |||||||||||||
APU L3 cache associativity (ways) | 16 | 16 | ||||||||||||||||
L3 cache scheme | Victim | N/A | Victim | Victim | ||||||||||||||
Max stock DRAM support | DDR3-1866 | DDR3-2133 | DDR3-2133, DDR4-2400 | DDR4-2400 | DDR4-2933 | DDR4-3200, LPDDR4-4266 | DDR3L-1333 | DDR3L-1600 | DDR3L-1866 | DDR3-1866, DDR4-2400 | DDR4-2400 | |||||||
Max DRAM channels per APU | 2 | 1 | 2 | |||||||||||||||
Max stock DRAM bandwidth (GB/s) per APU | 29.866 | 34.132 | 38.400 | 46.932 | 68.256 | 10.666 | 12.800 | 14.933 | 19.200 | 38.400 | ||||||||
GPU microarchitecture | TeraScale 2 (VLIW5) | TeraScale 3 (VLIW4) | GCN 2nd gen | GCN 3rd gen | GCN 5th gen[5] | TeraScale 2 (VLIW5) | GCN 2nd gen | GCN 3rd gen[5] | GCN 5th gen | |||||||||
GPU instruction set | TeraScale instruction set | GCN instruction set | TeraScale instruction set | GCN instruction set | ||||||||||||||
Max stock GPU base clock (MHz) | 600 | 800 | 844 | 866 | 1108 | 1250 | 1400 | 2100 | 538 | 600 | ? | 847 | 900 | 1200 | ||||
Max stock GPU base GFLOPS[lower-alpha 6] | 480 | 614.4 | 648.1 | 886.7 | 1134.5 | 1760 | 1971.2 | 2150.4 | 86 | ? | ? | ? | 345.6 | 460.8 | ||||
3D engine[lower-alpha 7] | Up to 400:20:8 | Up to 384:24:6 | Up to 512:32:8 | Up to 704:44:16[6] | Up to 512:?:? | 80:8:4 | 128:8:4 | Up to 192:?:? | Up to 192:?:? | |||||||||
IOMMUv1 | IOMMUv2 | IOMMUv1 | ? | IOMMUv2 | ||||||||||||||
Video decoder | UVD 3.0 | UVD 4.2 | UVD 6.0 | VCN 1.0[7] | UVD 3.0 | UVD 4.0 | UVD 4.2 | UVD 6.0 | UVD 6.3 | VCN 1.0 | ||||||||
Video encoder | N/A | VCE 1.0 | VCE 2.0 | VCE 3.1 | N/A | VCE 2.0 | VCE 3.1 | |||||||||||
GPU power saving | PowerPlay | PowerTune | PowerPlay | PowerTune[8] | ||||||||||||||
TrueAudio | N/A | ![]() | N/A | ![]() | ||||||||||||||
FreeSync | 1 2 | 1 2 | ||||||||||||||||
HDCP[lower-alpha 8] | ? | 1.4 | 1.4 2.2 | ? | 1.4 | 1.4 2.2 | ||||||||||||
PlayReady[lower-alpha 8] | N/A | 3.0 not yet | N/A | 3.0 not yet | ||||||||||||||
Supported displays[lower-alpha 9] | 2–3 | 2–4 | 3 | 3 (desktop) 4 (mobile, embedded) | 4 | 2 | 3 | 4 | ||||||||||
/drm/radeon [lower-alpha 10][11][12] | ![]() | N/A | ![]() | N/A | ||||||||||||||
/drm/amdgpu [lower-alpha 10][13] | N/A | ![]() | ![]() | N/A | ![]() | ![]() |
- APU models: A8-7680, A6-7480. CPU only: Athlon X4 845.
- A PC would be one node.
- An APU combines a CPU and a GPU. Both have cores.
- Requires firmware support.
- No SSE4. No SSSE3.
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
- Unified shaders : texture mapping units : render output units
- To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
- To feed more than two displays, the additional panels must have native DisplayPort support.[10] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
- DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.
See also
- List of AMD Accelerated Processing Unit microprocessors
- List of AMD mobile microprocessors
External links
- "49125_15h_Models_30h-3Fh_BKDG" (pdf). AMD.
- "AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. Retrieved 3 January 2020.
- "AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015.
- "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017.
- "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017.
- Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018.
- Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.
- Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 13 August 2016
- "A technical look at AMD's Kaveri architecture". Semi Accurate. Retrieved 6 July 2014.
- "How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. Retrieved 8 December 2014.
- Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". Retrieved 16 January 2016.
- "Radeon feature matrix". freedesktop.org. Retrieved 10 January 2016.
- Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU" (PDF). Retrieved 16 January 2016.
- Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org.