Intel 8008

The Intel 8008 ("eight-thousand-eight" or "eighty-oh-eight") is an early byte-oriented microprocessor designed and manufactured by Intel and introduced in April 1972. It is an 8-bit CPU with an external 14-bit address bus that could address 16 KB of memory. Originally known as the 1201, the chip was commissioned by Computer Terminal Corporation (CTC) to implement an instruction set of their design for their Datapoint 2200 programmable terminal. As the chip was delayed and did not meet CTC's performance goals, the 2200 ended up using CTC's own TTL-based CPU instead. An agreement permitted Intel to market the chip to other customers after Seiko expressed an interest in using it for a calculator.

Intel 8008
An Intel C8008-1 processor variant with purple ceramic, a gold metal lid, and gold pins.
General Info
Launchedmid 1972
Discontinued1983[1]
Common manufacturer(s)
  • Intel
Performance
Max. CPU clock rate200 kHz to 800 kHz
Data width8 Bit
Address width14 Bit
Architecture and classification
ApplicationComputer terminals, calculators, bottling machines, 1970s ASEA industrial robots[2] (IRB 6), simple computers, etc.
Min. feature size10 µm
Instruction set8008
Physical specifications
Transistors
  • 3,500
Package(s)
Socket(s)
History
SuccessorIntel 8080

History

CTC formed in San Antonio in 1968 under the direction of Austin O. "Gus" Roche and Phil Ray, both NASA engineers. Roche, in particular, was primarily interested in producing a desktop computer. However, given the immaturity of the market, the company's business plan mentioned only a Teletype Model 33 ASR replacement, which shipped as the Datapoint 3300. The case was deliberately designed to fit in the same space as an IBM Selectric typewriter and used a video screen shaped to have the same aspect ratio as an IBM punched card.[3] Although commercially successful, the 3300 had ongoing heat problems due to the amount of circuitry packed into such a small space.

In order to address the heating and other issues, a re-design started that featured the CPU part of the internal circuitry re-implemented on a single chip. Looking for a company able to produce their chip design, Roche turned to Intel, then primarily a vendor of memory chips.[3] Roche met with Bob Noyce, who expressed concern with the concept; John Frassanito recalls that "Noyce said it was an intriguing idea, and that Intel could do it, but it would be a dumb move. He said that if you have a computer chip, you can only sell one chip per computer, while with memory, you can sell hundreds of chips per computer."[3] Another major concern was that Intel's existing customer base purchased their memory chips for use with their own processor designs; if Intel introduced their own processor, they might be seen as a competitor, and their customers might look elsewhere for memory. Nevertheless, Noyce agreed to a $50,000 development contract in early 1970. Texas Instruments (TI) was also brought in as a second supplier.

TI was able to make samples of the 1201 based on Intel drawings, but these proved to be buggy and were rejected. Intel's own versions were delayed. CTC decided to re-implement the new version of the terminal using discrete TTL instead of waiting for a single-chip CPU. The new system was released as the Datapoint 2200 in the spring 1970, with their first sale to General Mills on May 25, 1970.[3] CTC paused development of the 1201 after the 2200 was released, as it was no longer needed. Six months later, Seiko approached Intel, expressing an interest in using the 1201 in a scientific calculator, likely after seeing the success of the simpler Intel 4004 used by Busicom in their business calculators. A small re-design followed, under the leadership of Federico Faggin, the designer of the 4004, now project leader of the 1201, expanding from a 16-pin to 18-pin design, and the new 1201 was delivered to CTC in late 1971.[3]

By that point, CTC had once again moved on, this time to the Datapoint 2200 II, which was faster. The 1201 was no longer powerful enough for the new model. CTC voted to end their involvement with the 1201, leaving the design's intellectual property to Intel instead of paying the $50,000 contract. Intel renamed it the 8008 and put it in their catalog in April 1972 priced at $120. Intel's initial worries about their existing customer base leaving them proved unfounded, and the 8008 went on to be a commercially successful design. This was followed by the Intel 8080, and then the hugely successful Intel x86 family.[3]

One of the first teams to build a complete system around the 8008 was Bill Pentz' team at California State University, Sacramento. The Sac State 8008 was possibly the first true microcomputer, with a disk operating system built with IBM Basic assembly language in PROM, all driving a color display, hard drive, keyboard, modem, audio/paper tape reader and printer.[4] The project started in the spring of 1972, and with key help from Tektronix the system was fully functional a year later. Bill assisted Intel with the MCS-8 kit and provided key input to the Intel 8080 instruction set, which helped make it useful for the industry and hobbyists.

In the UK, a team at S. E. Laboratories Engineering (EMI) led by Tom Spink in 1972 built a microcomputer based on a pre-release sample of the 8008. Joe Hardman extended the chip with an external stack. This, among other things, gave it power-fail save and recovery. Joe also developed a direct screen printer. The operating system was written using a meta-assembler developed by L. Crawford and J. Parnell for a Digital Equipment Corporation PDP-11.[5] The operating system was burnt into a PROM. It was interrupt-driven, queued, and based on a fixed page size for programs and data. An operational prototype was prepared for management, who decided not to continue with the project.

The 8008 was the CPU for the very first commercial non-calculator personal computers (excluding the Datapoint 2200 itself): the US SCELBI kit and the pre-built French Micral N and Canadian MCM/70. It was also the controlling microprocessor for the first several models in Hewlett-Packard's 2640 family of computer terminals.

Intel offered an instruction set simulator for the 8008 named INTERP/8. It was written in FORTRAN.

Design
i8008 microarchitecture
Intel 8008 registers
13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position)
Main registers
  A Accumulator
  B B register
  C C register
  D D register
  E E register
  H H register (indirect)
  L L register (indirect)
Program counter
PC Program Counter
Push-down address call stack
AS Call level 1
AS Call level 2
AS Call level 3
AS Call level 4
AS Call level 5
AS Call level 6
AS Call level 7
Status register
  C P Z S Flags

The 8008 was implemented in 10 μm silicon-gate enhancement-mode PMOS logic. Initial versions could work at clock frequencies up to 0.5 MHz. This was later increased in the 8008-1 to a specified maximum of 0.8 MHz. Instructions took between 5 and 11 T-states, where each T-state was 2 clock cycles.[6] Register–register loads and ALU operations took 5T (20 μs at 0.5 MHz), register–memory 8T (32 μs), while calls and jumps (when taken) took 11 T-states (44 μs).[7] The 8008 was a little slower in terms of instructions per second (36,000 to 80,000 at 0.8 MHz) than the 4-bit Intel 4004 and Intel 4040.[8] The fact that the 8008 processed data 8 bits at a time and could access significantly more RAM still gave it a significant speed advantage in most applications. The 8008 had 3,500 transistors.[9][10][11]

The chip (limited by its 18-pin DIP packaging) had a single 8-bit bus and required a significant amount of external support logic. For example, the 14-bit address, which could access "16 K × 8 bits of memory", needed to be latched by some of this logic into an external memory address register (MAR). The 8008 could access 8 input ports and 24 output ports.[6]

For controller and CRT terminal use, this was an acceptable design, but it was rather cumbersome to use for most other tasks, at least compared to the next generations of microprocessors. A few early computer designs were based on it, but most would use the later and greatly improved Intel 8080 instead.

The subsequent 40-pin NMOS Intel 8080 expanded upon the 8008 registers and instruction set and implemented a more efficient external bus interface (using the 22 additional pins). Despite a close architectural relationship, the 8080 was not made binary compatible with the 8008, so an 8008 program would not run on an 8080. However, as two different assembly syntaxes were used by Intel at the time, the 8080 could be used in an 8008 assembly-language backward-compatible fashion.[12]

The Intel 8085 was an electrically modernized version of the 8080 that used depletion-mode transistors and also added two new instructions.[13]

The Intel 8086, the original x86 processor, was a non-strict extension of the 8080, so it loosely resembled the original Datapoint 2200 design as well. Almost every Datapoint 2200 and 8008 instruction has an equivalent not only in the instruction set of the 8080, 8085, and Z80, but also in the instruction set of modern x86 processors (although the instruction encodings are different).[14]

Features

The 8008 architecture includes the following features:

  • Seven 8-bit "scratchpad" registers: The main accumulator (A) and six other registers (B, C, D, E, H, and L).
  • 14-bit program counter (PC).
  • Seven-level push-down address call stack. Eight registers are actually used, with the top-most register being the PC.
  • Four condition code status flags: carry (C), even parity (P), zero (Z), and sign (S).
  • Indirect memory access using the H and L registers (HL) as a 14-bit data pointer (the upper two bits are ignored).

Example code

The following 8008 assembly source code is for a subroutine named MEMCPY that copies a block of data bytes of a given size from one location to another.

                   
                   
                   
                   
                   
                   
                   
                   
                   
001700  000        
001701  000        
001702  000        
001703  000        
001704  000        
001705  000        
                   
                   
002000  066 304    
002002  056 003    
002004  327        
002005  060        
002006  317        
002007  302        
002010  261        
002011  053        
002012  302        
002013  024 001    
002015  320        
002016  301        
002017  034 000    
002021  310        
002022  066 300    
002024  056 003    
002026  347        
002027  060        
002030  337        
002031  302        
002032  206        
002033  360        
002034  301        
002035  215        
002036  350        
002037  307        
002040  066 302    
002042  056 003    
002044  347        
002045  060        
002046  337        
002047  364        
002050  353        
002051  330        
002052  302        
002053  206        
002054  360        
002055  301        
002056  215        
002057  350        
002060  373        
002061  104 007 004
002064             

; MEMCPY --
; Copy a block of memory from one location to another.
;
; Entry parameters
;       SRC: 14-bit address of source data block
;       DST: 14-bit address of target data block
;       CNT: 14-bit count of bytes to copy
 
            ORG     1700Q       ;Data at 001700q
SRC         DFB     0           ;SRC, low byte
            DFB     0           ;     high byte
DST         DFB     0           ;DST, low byte
            DFB     0           ;     high byte
CNT         DFB     0           ;CNT, low byte
            DFB     0           ;     high byte
 
            ORG     2000Q       ;Code at 002000q
MEMCPY      LLI     CNT+0       ;HL = addr(CNT)
            LHI     CNT+1
            LCM                 ;BC = CNT
            INL
            LBM
LOOP        LAC                 ;If BC = 0,
            ORB
            RTZ                 ;Return
DECCNT      LAC                 ;BC = BC - 1
            SUI     1
            LCA
            LAB
            SBI     0
            LBA
GETSRC      LLI     SRC+0       ;HL = addr(SRC)
            LHI     SRC+1
            LEM                 ;DE = SRC
            INL
            LDM
            LAC                 ;HL = DE + BC
            ADE
            LLA
            LAB
            ACD
            LHA
            LAM                 ;Load A from (HL)
GETDST      LLI     DST+0       ;HL = addr(DST)
            LHI     DST+1
            LEM                 ;DE = DST
            INL
            LDM
            LLE                 ;HL = DE
            LHD
            LDA                 ;D = A
            LAC                 ;HL = HL + BC
            ADL
            LLA
            LAB
            ACH
            LHA
            LMD                 ;Store D to (HL)
            JMP     LOOP        ;Repeat the loop
            END

In the code above, all values are given in octal. Locations SRC, DST, and CNT are 16-bit parameters for the subroutine named MEMCPY. In actuality, only 14 bits of the values are used, since the CPU has only a 14-bit addressable memory space. The values are stored in little-endian format, although this is an arbitrary choice, since the CPU is incapable of reading or writing more than a single byte into memory at a time. Since there is no instruction to load a register directly from a given memory address, the HL register pair must first be loaded with the address, and the target register can then be loaded from the M operand, which is an indirect load from the memory location in the HL register pair. The BC register pair is loaded with the CNT parameter value and decremented at the end of the loop until it becomes zero. Note that most of the instructions used occupy a single 8-bit opcode.

Designers
  • CTC (Instruction set and architecture): Victor Poor and Harry Pyle.
  • Intel (Implementation in silicon):
    • Ted Hoff, Stan Mazor and Larry Potter (IBM Chief Scientist) proposed a single-chip implementation of the CTC architecture, using RAM-register memory rather than shift-register memory, and also added a few instructions and interrupt facility. The 8008 (originally called 1201) chip design started before the 4004 development. Hoff and Mazor, however, could not and did not develop a "silicon design" because they were neither chip designers nor process developers, and furthermore the necessary silicon-gate-based design methodology and circuits, under development by Federico Faggin for the 4004, were not yet available.[15]
    • Federico Faggin, having finished the design of the 4004, became leader of the project from January 1971 until its successful completion in April 1972, after it had been suspended – for lack of progress – for about seven months.
    • Hal Feeney, project engineer, did the detailed logic design, circuit design, and physical layout under Faggin's supervision, employing the same design methodology that Faggin had originally developed for the Intel 4004 microprocessor, and utilizing the basic circuits he had developed for the 4004. A combined "HF" logo was etched onto the chip about halfway between the D5 and D6 bonding pads.

Second sources
gollark: Updated the network security page a bit.
gollark: A table.
gollark: It's necessary and removing it would make rednet not rednet as much as "slightly packeted modem".
gollark: With maybe 8 modems you can cycle rapidly through channels listening for used ones then listen on those.
gollark: You don't even *need* one.

See also
  • Mark-8, an 8008-based computer kit

References
  1. CPU History – The CPU Museum – Life Cycle of the CPU.
  2. "Thirty years in robotics - Robotics". archive.org. March 19, 2014. Retrieved April 11, 2018.
  3. Wood, Lamont (August 8, 2008), "Forgotten PC history: The true origins of the personal computer", Computerworld
  4. "Inside the world's long-lost first microcomputer". cnet.com. January 8, 2010. Retrieved April 11, 2018.
  5. Brunel University, 1974. Master of Technology dissertation, L. R. Crawford.
  6. "MCS-8 Micro Computer Set Users Manual" (PDF). Intel Corporation. 1972. Retrieved December 4, 2010.
  7. "Intel 8008 Opcodes". Retrieved December 4, 2010.
  8. "Intel 8008 (i8008) microprocessor family". CPU World. 2003–2010. Retrieved December 4, 2010.
  9. Intel. "Gordon Moore and Moore's Law". Archived from the original on September 4, 2009. Retrieved June 28, 2009.
  10. Intel (2012). "Intel Chips: timeline poster".
  11. Intel (2008). "Microprocessor Quick Reference Guide".
  12. See the Z80 article for a description.
  13. See the Intel 8085 article for a description.
  14. See the Intel 8086 article for a description.
  15. Faggin, Federico; Hoff, Marcian E.; Mazor, Stanley; Shima, Masatoshi (December 1996), "The History of the 4004", IEEE Micro, Los Alamitos: IEEE Computer Society, 16 (6): 10–19, doi:10.1109/40.546561, ISSN 0272-1732
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