HiSilicon

HiSilicon (Chinese: 海思; pinyin: Hǎisī) is a Chinese fabless semiconductor company based in Shenzhen, Guangdong and fully owned by Huawei. HiSilicon purchases licenses for CPU designs from ARM Holdings, including the ARM Cortex-A9 MPCore, ARM Cortex-M3, ARM Cortex-A7 MPCore, ARM Cortex-A15 MPCore,[2][3] ARM Cortex-A53, ARM Cortex-A57 and also for their Mali graphics cores.[4][5] HiSilicon has also purchased licenses from Vivante Corporation for their GC4000 graphics core.

HiSilicon Co., Ltd.
Native name
海思半导体有限公司
Subsidiary
IndustryFabless semiconductors, Semiconductors, Integrated circuit design
Founded1991 (1991)[1]
HeadquartersShenzhen, Guangdong, China
ProductsSoCs
BrandsKirin
ParentHuawei
Websitewww.hisilicon.com
HiSilicon
Simplified Chinese海思半导体有限公司
Traditional Chinese海思半導體有限公司
Literal meaningHaisi Semiconductor Limited Company

HiSilicon is reputed to be the largest domestic designer of integrated circuits in China.[6] In 2020, the U.S. instituted rules that require American firms providing certain equipment to HiSilicon to have licenses[7] and announced it will stop producing its Kirin chipset from september 15, 2020 onwards.[8]

Smartphone application processors

HiSilicon develops SoCs based on ARM architecture. Though not exclusive, these SoCs see preliminary use in handheld and tablet devices of its parent company Huawei.

K3V2

The first well known product of HiSilicon is the K3V2 used in Huawei Ascend D Quad XL (U9510) smartphones[9] and Huawei MediaPad 10 FHD7 tablets. This chipset is based on the ARM Cortex-A9 MPCore fabbed at 40 nm and uses a 16 core Vivante GC4000 GPU.[10] The SoC supports LPDDR2-1066, but actual products are found with LPDDR-900 instead for lower power consumption.

Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
K3V2 (Hi3620) 40 nm ARMv7 Cortex-A9 L1: 32 KB instruction + 32 KB data, L2: 1 MB41.4 Vivante GC4000240 MHz

(15.3GFlops)

 LPDDR264-bit dual-channel7.2 (up to 8.5) N/AN/AN/AN/A Q1 2012

K3V2E

This is a revised version of K3V2 SoC with improved support of Intel baseband. The SoC supports LPDDR2-1066, but actual products are found with LPDDR-900 instead for lower power consumption.

Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
K3V2E 40 nm ARMv7 Cortex-A9 L1: 32 KB instruction + 32 KB data, L2: 1 MB41.5 Vivante GC4000240 MHz

(15.3GFlops)

 LPDDR264-bit dual-channel7.2 (up to 8.5) N/AN/AN/AN/A 2013

Kirin 620

• supports – USB 2.0 / 13 MP / 1080p video encode

Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 620 28 nm ARMv8-A Cortex-A53 4 1.2 Mali-450 MP4 533 MHz (32GFlops) LPDDR3 ( MHz)32-bit single-channel6.4 N/A Dual SIM LTE Cat.4 (150 Mbit/s)802.11 b/g/n (Wifi Direct & Hotspot) Not Supporting DLNA / MiracastBluetooth v4.0, A2DP, EDR, LE Q1 2015

Kirin 650, 655, 658, 659
Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 650 16 nm FinFET+ ARMv8-A Cortex-A53
Cortex-A53		 4+4 2.0 (4xA53) 1.7 (4xA53) Mali-T830 MP2 900 MHz

(40.8GFlops)

 LPDDR3 (933 MHz)64-bit dual-channel (2x32bit)[11] A-GPS, GLONASS Dual SIM LTE Cat.6 (300 Mbit/s)802.11 b/g/nBluetooth v4.1 Q2 2016
Kirin 655 2.12 (4xA53) 1.7 (4xA53) Q4 2016
Kirin 658 2.35 (4xA53) 1.7 (4xA53) 802.11 b/g/n/ac Q2 2017
Kirin 659 2.36 (4xA53) 1.7 (4xA53) 802.11 b/g/nBluetooth v4.2 Q3 2017

Kirin 710
Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 710 12 nm FinFET by TSMC ARMv8-A Cortex-A73
Cortex-A53		 4+4 2.2 (A73)

1.7 (A53)

 Mali-G51 MP4 1000 MHz LPDDR3 LPDDR432-bit A-GPS, GLONASS Dual SIM LTE Cat.12 (600 Mbit/s)802.11 b/g/nBluetooth v4.2 Q3 2018
Kirin 710F[12]
Kirin 710A 14 nm FinFET by SMIC[13] 2.0 (A73)

? (A53)

Kirin 810 and 820
  • DaVinci NPU based on Tensor Arithmetic Unit
  • Kirin 820 supported 5G NSA & SA
Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 810 7 nm FinFET ARMv8.2-A Cortex-A76
Cortex-A55
DynamIQ		 2+6 2.27 (2xA76)
1.9 (6xA55)		 Mali-G52 MP6 820 MHz LPDDR4X (2133 MHz)64-bit (16-bit quad-channel) 31.78 A-GPS, GLONASS, BDS Dual SIM LTE Cat.12 (600 Mbit/s)802.11 b/g/n/acBluetooth v5.0 Q2 2019
Kirin 820 5G (1+3)+4 2.36 (1xA76 H)
2.22 (3xA76 L)
1.84 (4xA55)		 Mali-G57 MP6 Balong 5000 (Sub-6GHz Only; NSA & SA) Q1 2020

Kirin 910 and 910T
Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 910 28 nm HPM ARMv7 Cortex-A941.6 Mali-450 MP4533 MHz

(32GFlops)

 LPDDR332-bit single-channel6.4 N/A LTE Cat.4N/AN/A H1 2014
Kirin 910T 1.8 700 MHz

(41.8GFlops)

 N/AN/AN/A H1 2014

Kirin 920, 925 and 928

• The Kirin 920 SoC also contains an image processor that supports up to 32-megapixel

Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 920 28 nm HPM ARMv7 Cortex-A15
Cortex-A7
big.LITTLE		4+41.7 (A15)
1.3 (A7)		 Mali-T628 MP4600 MHz

(76.8GFlops)

 LPDDR3 (1600 MHz)64-bit dual-channel12.8 N/A LTE Cat.6 (300 Mbit/s)N/AN/A H2 2014
Kirin 925 1.8 (A15)
1.3 (A7)		 N/AN/AN/A Q3 2014
Kirin 928 2.0 (A15)
1.3 (A7)		 N/AN/A N/A N/A

Kirin 930 and 935

• supports – SD 3.0 (UHS-I) / eMMC 4.51 / Dual-band a/b/g/n Wi-Fi / Bluetooth 4.0 Low Energy / USB 2.0 / 32 MP ISP / 1080p video encode

Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 930 28 nm HPC ARMv8-A Cortex-A53
Cortex-A53		 4+4 2.0 (A53)
1.5 (A53)		 Mali-T628 MP4 600 MHz

(76.8GFlops)

 LPDDR3 (1600 MHz)64-bit(2x32-bit) Dual-channel12.8 GB/s N/A Dual SIM LTE Cat.6 (DL:300 Mbit/s UP:50 Mbit/s)N/AN/A Q1 2015
Kirin 935 2.2 (A53)
1.5 (A53)		 680 MHz

(87GFlops)

 N/AN/AN/A Q1 2015

Kirin 950 and 955

• supports – SD 4.1 (UHS-II) / UFS 2.0 / eMMC 5.1 / MU-MIMO 802.11ac Wi-Fi / Bluetooth 4.2 Smart / USB 3.0 / NFS / Dual ISP (42 MP) / Native 10-bit 4K video encode / i5 coprocessor / Tensilica HiFi 4 DSP

Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 950 TSMC 16 nm FinFET+[18] ARMv8-A Cortex-A72
Cortex-A53
big.LITTLE		 4+4 2.3 (A72)
1.8 (A53)		 Mali-T880 MP4 900 MHz

(122.4GFlops)

 LPDDR464-bit(2x32-bit) Dual-channel25.6 N/A Dual SIM LTE Cat.6N/AN/A Q4 2015
Kirin 955[20] 2.5 (A72)
1.8 (A53)		 LPDDR3 (3 GB) LPDDR4 (4 GB) N/AN/AN/A Q2 2016

Kirin 960
  • Interconnect: ARM CCI-550, Storage: UFS 2.1, eMMC 5.1, Sensor Hub: i6
Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 960[21] TSMC 16 nm FFC ARMv8-A Cortex-A73
Cortex-A53
big.LITTLE		 4+4 2.36 (A73)
1.84 (A53)		 Mali-G71 MP8 1037 MHz

(282GFlops)

 LPDDR4-160064-bit(2x32-bit) Dual-channel28.8 N/A Dual SIM LTE Cat.12 LTE 4x CA, 4x4 MIMON/AN/A Q4 2016

Kirin 970
  • Interconnect: ARM CCI-550, Storage: UFS 2.1, Sensor Hub: i7
  • Cadence Tensilica Vision P6 DSP.[22]
  • NPU made in collaboration with Cambricon Technologies. 1.92T FP16 OPS.[23]
Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 970 TSMC 10 nm FinFET+ ARMv8-A Cortex-A73
Cortex-A53
big.LITTLE		 4+4 2.36 (A73)
1.84 (A53)		 Mali-G72 MP12 746 MHz

(330 GFlops)

 LPDDR4X-186664-bit(4x16-bit) Quad-channel29.8 Galileo Dual SIM LTE Cat.18 LTE 5x CA, No 4x4 MIMON/AN/A Q4 2017

Kirin 980

It is HiSilicon's first SoC based on 7 nm FinFET technology.

  • Interconnect: ARM Mali G76-MP10, Storage: UFS 2.1, Sensor Hub: i8
  • Dual NPU made in collaboration with Cambricon Technologies.
Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 980 TSMC 7 nm FinFET ARMv8.2-A Cortex-A76
Cortex-A55
DynamIQ		 (2+2)+4 2.6 (A76 H)
1.92 (A76 L)
1.8 (A55)		 Mali-G76 MP10 720 MHz

(489.6 GFlops)[24]

 LPDDR4X-213364-bit(4x16-bit) Quad-channel34.1 Galileo Dual SIM LTE Cat.21 LTE 5x CA, No 4x4 MIMON/AN/A Q4 2018

Kirin 985 5G

It is HiSilicon's second 5G SoC based on 7 nm FinFET technology.

  • Interconnect : ARM Mali-G77 MP8
  • Big-Tiny Core Da Vinci NPU
Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 985 5G TSMC 7 nm FinFET ARMv8.2-A Cortex-A76
Cortex-A55
DynamIQ		 (1+3)+4 2.58 (A76 H)
2.40 (A76 L)
1.84 (A55)		 Mali-G77 MP8 ? LPDDR4X-2133 64-Bit(4x16-Bit) Quad-Channel 34.1 Galileo Balong 5000 (Sub-6GHz only; NSA & SA) N/A N/A Q2 2020

Kirin 990 4G & 990 5G

Kirin 990 5G is HiSilicon's first SoC based on N7 nm+ FinFET technology.[25]

  • Interconnect: ARM Mali-G76 MP16
  • Da Vinci NPU.
    • Kirin 990 4G: 1x Da Vinci Lite + 1x Da Vinci Tiny
    • Kirin 990 5G: 2x Da Vinci Lite + 1x Da Vinci Tiny
  • Da Vinci Lite features 3D Cube Tensor Computing Engine (2048 FP16 MACs + 4096 INT8 MACs), Vector unit (1024bit INT8/FP16/FP32)
  • Da Vinci Tiny features 3D Cube Tensor Computing Engine (256 FP16 MACs + 512 INT8 MACs), Vector unit (256bit INT8/FP16/FP32)[26]
Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 990 4G TSMC 7 nm FinFET (DUV) ARMv8.2-A Cortex-A76
Cortex-A55
DynamIQ		 (2+2)+4 2.86 (A76 H)
2.09 (A76 L)
1.86 (A55)		 Mali-G76 MP16 600 MHz
(737.28 GFLOPS)		 LPDDR4X-213364-bit(4x16-bit) Quad-channel34.1 Galileo Balong 765 (LTE Cat.19)N/AN/A Q4 2019
Kirin 990 5G TSMC 7 nm+ FinFET (EUV) 2.86 (A76 H)
2.36 (A76 L)
1.95 (A55)		 Balong 5000 (Sub-6-GHz only; NSA & SA)N/A N/A

Smartphone modems

HiSilicon develops smartphone modems which although not exclusively, these SoCs see preliminary use in handheld and tablet devices of its parent company Huawei.

Balong 700

The Balong 700 supports LTE TDD/FDD.[27] Its specs:

  • 3GPP R8 protocol
  • LTE TDD and FDD
  • 4x2/2x2 SU-MIMO

Balong 710

At MWC 2012 HiSilicon released the Balong 710.[28] It is a multi-mode chipset supporting 3GPP Release 9 and LTE Category 4 at GTI (Global TD-LTE Initiative). The Balong 710 was designed to be used with the K3V2 SoC. Its specs:

  • LTE FDD mode : 150 Mbit/s downlink and 50 Mbit/s uplink.
  • TD-LTE mode: up to 112 Mbit/s downlink and up to 30 Mbit/s uplink.
  • WCDMA Dual Carrier with MIMO: 84Mbit/s downlink and 23Mbit/s uplink.

Balong 720

The Balong 720 supports LTE Cat6 with 300 Mbit/s peak download rate.[27] Its specs:

  • TSMC 28 nm HPM process
  • TD-LTE Cat.6 standard
  • Dual-carrier aggregation for the 40 MHz bandwidth
  • 5-mode LTE Cat6 Modem

Balong 750

The Balong 750 supports LTE Cat 12/13, and it is first to support 4CC CA and 3.5 GHz.[27] Its specs:

  • LTE Cat.12 and Cat.13 UL network standards
  • 2CC (dual-carrier) data aggregation
  • 4x4 multiple-input multiple-output (MIMO)
  • TSMC 16 nm FinFET+ process

Balong 765

The Balong 765 supports 8×8 MIMO technology, LTE Cat.19 with downlink data-rate up to 1.6 Gbit/s in FDD network and up to 1.16 Gbit/s in the TD-LTE network.[29] Its specs:

  • 3GPP Rel.14
  • LTE Cat.19 Peak data rate up to 1.6 Gbit/s
  • 4CC CA + 4×4 MIMO/2CC CA + 8×8 MIMO
  • DL 256QAM
  • C-V2X

Balong 5G01

The Balong 5G01 supports the 3GPP standard for 5G with downlink speeds of up to 2.3 Gbit/s. It supports 5G across all frequency bands including sub-6 GHz and millimeter wave (mmWave).[27] Its specs:

  • 3GPP Release 15
  • Peak data rate up to 2.3 Gbit/s
  • Sub-6 GHz and mmWave
  • NSA/SA
  • DL 256QAM

Balong 5000

The Balong 5000 supports 2G, 3G, 4G, and 5G.[30] Its specs:

  • 2G/3G/4G/5G Multi Mode
  • Fully compliant with 3GPP Release 15
  • Sub-6 GHz: 100 MHz x 2CC CA
  • Sub-6 GHz:Downlink up to 4.6 Gbit/s, Uplink up to 2.5 Gbit/s
  • mmWave:Downlink up to 6.5 Gbit/s, Uplink up to 3.5 Gbit/s
  • NR+LTE:Downlink up to 7.5 Gbit/s
  • FDD & TDD Spectrum Access
  • SA & NSA Fusion Network Architecture
  • Supports 3GPP R14 V2X
  • 3GB LPDDR4X[31]

Wearable SoCs

HiSilicon develops SoCs for wearables such as truly wireless earbuds, wireless headphones, neckband earbuds, smart speakers, smart eyewear and smartwatches.[32]

Kirin A1

The Kirin A1 was announced on September 6, 2019.[32] It features:

  • BT/BLE dual-mode Bluetooth 5.1[33]
  • Isochronous Dual Channel transmission technology
  • 356 MHz audio processor

Server processors

HiSilicon develops server processor SoCs based on ARM architecture.

Hi1610

The Hi1610 is HiSilicon's first generation server processor announced in 2015. It features:

  • 16x ARM Cortex-A57 at up to 2.1 GHz[34]
  • 48 KB L1-I, 32 KB L1-D, 1MB L2/4 cores and 16MB CCN L3
  • TSMC 16 nm
  • 2x DDR4-1866
  • 16 PCIe 3.0

Hi1612

The Hi1612 is HiSilicon's second generation server processor launched in 2016. It features:

  • 32x ARM Cortex-A57 at up to 2.1 GHz[34]
  • 48 KB L1-I, 32 KB L1-D, 1MB L2/4 cores and 32MB CCN L3
  • TSMC 16 nm
  • 4x DDR4-2133
  • 16 PCIe 3.0

Kunpeng 916 (formally Hi1616)

The Kunpeng 916 (formally known as Hi1616) is HiSilicon's third generation server processor launched in 2017. The Kunpeng 916 is utilized in Huawei's TaiShan 2280 Balanced Server, TaiShan 5280 Storage Server, TaiShan XR320 High-Density Server Node and TaiShan X6000 High-Density Server.[35][36][37][38] It features:

  • 32x Arm Cortex-A72 at up to 2.4 GHz[34]
  • 48 KB L1-I, 32 KB L1-D, 1MB L2/4 cores and 32MB CCN L3
  • TSMC 16 nm
  • 4x DDR4-2400
  • 2-way Symmetric multiprocessing (SMP), Each socket has 2x ports with 96 Gbit/s per port (total of 192 Gbit/s per each socket interconnects)
  • 46 PCIe 3.0 and 8x 10 GbE
  • 85 W

Kunpeng 920 (formally Hi1620)

The Kunpeng 920 (formally known as Hi1620) is HiSilicon's fourth generation server processor announced in 2018, launched in 2019. Huawei claim the Kunpeng 920 CPU scores more than an estimated 930 on SPECint®_rate_base2006.[39] The Kunpeng 920 is utilized in Huawei's TaiShan 2280 V2 Balanced Server, TaiShan 5280 V2 Storage Server and TaiShan XA320 V2 High-Density Server Node.[40][41][42] It features:

  • 32 to 64x custom TaiShan v110 cores at up to 2.6 GHz.[43]
  • The TaiShan v110 core is a 4-way out-of-order superscalar that implements the ARMv8.2-A ISA. Huawei reports the core supports almost all the ARMv8.4-A ISA features with a few exceptions, including dot product and the FP16 FML extension.[43]
  • The TaiShan v110 cores are likely a new core not based on ARM designs [44]
  • 3x Simple ALUs, 1x Complex MDU, 2x BRUs (sharing ports with ALU2/3), 2x FSUs (ASIMD FPU), 2x LSUs[44]
  • 64 KB L1-I, 64 KB L1-D, 512 KB Private L2 and 1MB L3/core Shared.
  • TSMC 7 nm HPC
  • 8x DDR4-3200
  • 2-way and 4-way Symmetric multiprocessing (SMP). Each socket has 3x Hydra ports with 240 Gbit/s per port (total of 720 Gbit/s per each socket interconnects)
  • 40 PCIe 4.0 with CCIX support, 4 USB 3.0, 2x SATA 3.0, x8 SAS 3.0 and 2 x 100 GbE
  • 100 to 200 W
  • Compression engine (GZIP, LZS, LZ4) capable of up to 40 Gib/s compress and 100 Gbit/s decompress
  • Crypto offload engine (for AES, DES, 3DES, SHA1/2, etc..) capable of throughputs up to 100 Gbit/s

Kunpeng 930 (formally Hi1630)

The Kunpeng 930 (formally known as Hi1630) is HiSilicon's fifth-generation server processor announced in 2019 and scheduled for launch in 2021. It features:

  • TBD custom cores with higher frequencies, support for simultaneous multithreading (SMT) and ARM's Scalable Vector Extension (SVE).[43]
  • 64 KB L1-I, 64 KB L1-D, 512 KB Private L2 and 1 MB L3/core Shared
  • TSMC 7 nm?
  • 8x DDR5

Kunpeng 950

The Kunpeng 950 is HiSilicon's sixth-generation server processor announced in 2019 and scheduled for launch in 2023.

AI acceleration

HiSilicon also develops AI Acceleration chips.

Da Vinci architecture

Each Da Vinci Max AI Core features a 3D Cube Tensor Computing Engine (4096 FP16 MACs + 8192 INT8 MACs), Vector unit (2048bit INT8/FP16/FP32) and scalar unit. It includes a new AI framework called "MindSpore", a platform-as-a-service product called ModelArts, and a lower-level library called Compute Architecture for Neural Networks (CANN).[26]

Ascend 310

The Ascend 310 is an AI inference SoC, it was codenamed Ascend-Mini. The Ascend 310 is capable of 16 TOPS@INT8 and 8 TOPS@FP16.[45] The Ascend 310 features:

  • 2x Da Vinci Max AI cores[26]
  • 8x ARM Cortex-A55 CPU cores
  • 8 MB on-chip buffer
  • 16 channel video decode – H.264/H.265
  • 1 channel video encode – H.264/H.265
  • TSMC 12 nm FFC process
  • 8 W

Ascend 910

The Ascend 910 is an AI training SoC, it was codenamed Ascend-Max. which delivers 256 TFLOPS@FP16 and 512 TOPS@INT8. The Ascend 910 features:

  • 32x Da Vinci Max AI cores arranged in 4 clusters[26]
  • 1024-bit NoC Mesh @ 2 GHz, with 128 GB/s bandwidth Read/Write per core
  • 3x 240Gbit/s HCCS ports for Numa connections
  • 2x 100Gbit/s RoCE interfaces for networking
  • 4x HBM2E, 1.2 TB/s bandwidth
  • 3D-SRAM stacked below AI SoC die
  • 1228 mm2 Total die size (456 mm2 Virtuvian AI SoC, 168 mm2 Nimbus V3 IO Die, 4x96mm 2 HBM2E, 2x110 mm2 Dummy Die)
  • 32 MB on-chip buffer
  • 128 channel video decode – H.264/H.265
  • TSMC 7+ nm EUV (N7+) process
  • 350 W

The Ascend 910 Cluster has 1024–2048 Ascend 910 chips to reach 256–512 petaFLOPS@FP16. The Ascend 910 and Ascend Cluster will be available in Q2 2019.[46]

Similar platforms

The Kirin processors compete with products from several other companies, including:

gollark: Yes.
gollark: There is proof of stake, which replaces the mining with "staking", where you just put up some coins for a bit and randomly get assigned more based on that. But this is also bad.
gollark: If you benefit from more computation *at all*, someone will just deploy 29383728929 computers doing the more efficient thing.
gollark: It is deliberately wasteful. It can't be useful work or something something side markets (I forgot).
gollark: Yes, but then you couldn't use mining to allocate new coins and make evilness with new blocks expensive.

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