Crossbar latch

The Crossbar Latch is a technology invented by Hewlett-Packard in October 2001, that HP claims could replace transistors in some applications. This would allow the construction of integrated circuits made entirely from memristors, which HP states could be simpler and less expensive to build. HP says that it is possible for memristors to eventually replace transistors in the way that transistors replaced the vacuum tube. [1]

Not to be confused with crossbar switch.

Details

The crossbar was introduced by Hewlett-Packard scientists in the Journal of Applied Physics, which provides a basis for constructing logic gates using memristors. The crossbar latch consists of a signal line crossed by two control lines. Depending on the voltages sent down the various lines, it can simulate the action of the three major logic gates: AND, OR and NOT.

The abstract of the patent is as follows:

"A molecular crossbar latch is provided, comprising two control wires and a signal wire that crosses the two control wires at a non-zero angle to thereby form a junction with each control wire. Each junction forms a switch and the junction has a functional dimension in nanometers. The signal wire selectively has at least two different voltage states, ranging from a 0 state to a 1 state, wherein there is an asymmetry with respect to the direction of current flow from the signal wire through one junction compared to another junction such that current flowing through one junction into (out of) the signal wire can open (close) while current flowing through the other junction out of (into) the signal wire can close (open) the switch, and wherein there is a voltage threshold for switching between an open switch and a closed switch. Further, methods are provided for latching logic values onto nanowires in a logic array, for inverting a logic value, and for restoring a voltage value of a signal in a nano-scale wire. Invented by Phillip J Kuekes."

— U.S. patent 6,586,965[2]

Applications in arithmetic processing
Fig. 1 Crossbar latches configured as a half-adder

This application was developed by Greg Snider of Hewlett-Packard and employs crossbar latches to replicate the functions of a half adder, which form the basis of modern computational architectures.[3] In this application a crossbar tile is formed of a layer of horizontal row wires and a layer of vertical column wires in which memristor or similar materials are sandwiched between the horizontal and vertical wire layers. Each intersection or junction of the crossbar tile is configurable to be at a high-resistance state in which there is little or no current between the horizontal and vertical wires or at a low-resistance state in which current is permitted. Fig. 1 illustrates the configuration of a half-adder using a crossbar tile, as taught by Snider, with the nodes identifying junctions of the crossbar tile configured as low-resistance states. By setting different logic inputs A, NOT A, B, and NOT B to different row wires this configuration produces the sum and carry outputs typical for a half-adder. Connections between multiple half-adders may then be used to form full adders in accordance with conventional arithmetic architectures.

Applications of crossbar latch in neuromorphics

Crossbar latches have been suggested as components of neuromorphic computing systems. One implementation of this is in the form of a neural network formed from nanowires as discussed in a patent by Greg Snider of Hewlett-Packard.[4]

gollark: Not sure it's massively relevant to the "bank" thing though.
gollark: You could develop your own (I mean `you` in the sense of the German `mann`, not actually you personally) but it would be annoying.
gollark: Pretty sure it is indeed closed-source.
gollark: <@186486131565527040> Your "help" tends to involve writing all the code for you.
gollark: `fs.ultradelete` is potatOS, gets around the recycle bin feature.

See also

References
  1. Singer, Michael. "HP's "Crossbar Latch' to Replace Transistors?". InternetNews.com. InternetNews.com. Retrieved 8 May 2015.
  2. "U.S. Patent 6,586,965".
  3. "U.S. Patent 7,203,789".
  4. "U.S. Patent 7,359,888".
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