Registered memory

Registered (also called buffered) memory modules have a register between the DRAM modules and the system's memory controller. They place less electrical load on the memory controller and allow single systems to remain stable with more memory modules than they would have otherwise. When compared with registered memory, conventional memory is usually referred to as unbuffered memory or unregistered memory. When manufactured as a dual in-line memory module (DIMM), a registered memory module is called an RDIMM, while unregistered memory is called UDIMM or simply DIMM.

Not to be confused with ECC memory, although memory modules often use both technologies.
Two 8 GB DDR4-2133 ECC 1.2 V registered DIMMs (RDIMMs)

Registered memory is often more expensive because of the lower number of units sold and additional circuitry required, so it is usually found only in applications where the need for scalability and robustness outweighs the need for a low price – for example, registered memory is usually used in servers.

Although most registered memory modules also feature error-correcting code memory (ECC), it is also possible for registered memory modules to not be error-correcting or vice versa. Unregistered ECC memory is supported and used in workstation or entry-level server motherboards that do not support very large amounts of memory.[1]

Performance

Normally, there is a performance penalty for using registered memory. Each read or write is buffered for one cycle between the memory bus and the DRAM, so the registered RAM can be thought of as running one clock cycle behind the equivalent unregistered DRAM. With SDRAM, this only applies to the first cycle of a burst.

However, this performance penalty is not universal. There are many other factors involved in memory access speed. For example, the Intel Westmere 5600 series of processors access memory using interleaving, wherein memory access is distributed across three channels. If two memory DIMMs are used per channel, this "results in a reduction of maximum memory bandwidth for 2DPC (DIMMs per channel) configurations with UDIMM by some 5% in comparison to RDIMM".[2] (p. 14). This occurs because "when you go to two DIMMs per memory channel, due to the high electrical loading on the address and control lines, the memory controller uses a '2T' or '2N' timing for UDIMMs. Consequently, every command that normally takes a single clock cycle is stretched to two clock cycles to allow for settling time.

Compatibility

Usually, the motherboard must match the memory type; as a result, registered memory will not work in a motherboard not designed for it, and vice versa. Some PC motherboards accept or require registered memory, but registered and unregistered memory modules cannot be mixed.[3] There is much confusion between registered and ECC memory; it is widely thought that ECC memory (which may or may not be registered) will not work at all in a motherboard without ECC support, not even without providing the ECC functionality, although the compatibility issues actually arise when trying to use registered memory (which also supports ECC and is described as ECC RAM) in a PC motherboard that does not support it.

Buffered memory

Registered (Buffered) DIMMs (R-DIMMs) insert a buffer between the command/address bus pins on the DIMM and the memory chips proper. A high-density DIMM might have 36 memory chips (assuming four ranks and ECC), each of which must receive the memory address, and their combined input capacitance limits the speed at which the memory bus can operate. By amplifying the signal on the DIMM, this allows more chips to be connected to the memory bus. The cost is one additional clock cycle of memory latency required for the address to traverse the additional buffer. Early registered RAM modules were physically incompatible with unregistered RAM modules, but SDRAM DIMMs are interchangeable, and some motherboards support both types.

Load Reduced DIMMs (LR-DIMMs) modules are similar, but add a buffer to the data lines as well. As a result, LRDIMM memory provides large overall maximum memory capacities, while avoiding the performance and power consumption problems of FB-DIMM memory.[4][5]

Fully Buffered DIMM (FB-DIMM) modules were an attempt to increase maximum memory capacities in large systems even more, using a more complex buffer chip to translate between the wide bus of standard SDRAM chips and a narrow, high-speed serial memory bus.[4] By reducing the number of pins required per memory bus, CPUs could support more memory buses, allowing higher total memory bandwidth. Unfortunately, the translation further increased memory latency, and the complex high-speed buffer chips used significant power, to the point that the resultant heat made FB-DIMMs unpopular in high-density servers (such as blade servers).

Both FB-DIMM and LR-DIMM memory types are designed primarily to control the amount of electric current flowing to and from the memory chips at any given time. They are not compatible with registered/buffered memory, and motherboards that require them usually will not accept any other kind of memory.

gollark: I'm considering somehow coordinating it with the *other* reactor which burns TBU oxide.
gollark: Otherwise it turns off.
gollark: Basically, the top one transmits the powercell's fullness level (obtained via a computercraft thing since comparators appear to not work) and the bottom one receives that, reads the reactor's buffer level (it was meant to be heat but somehow I just get the RF output buffer level), and if the powercell is below full and the buffer empty it turns the reactor on.
gollark: Some screenshots of the controllers.
gollark: TIS-100 is a weird massively-parallel architecture of nodes running simple assembly programs communicating with each other.

References
  1. "Servers and workstations: P9D-V motherboard". Asus. Retrieved December 4, 2014.
  2. https://globalsp.ts.fujitsu.com/dmsp/Publications/public/wp-westmere-ep-memory-performance-ww-en.pdf
  3. "Dell servers example" (PDF). Dell.
  4. "What is LR-DIMM, LRDIMM Memory? (Load-Reduce DIMM)". simmtester.com. Retrieved 2014-08-29.
  5. Johan De Gelas (2012-08-03). "LRDIMMs, RDIMMs, and Supermicro's Latest Twin". AnandTech. Retrieved 2014-09-09.
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