Process–architecture–optimization model

Process–architecture–optimization is a development model for central processing units (CPUs) that Intel adopted in 2016. Under this three-phase (three-year) model, every microprocessor die shrink is followed by a microarchitecture change and then by an optimization. It replaced the two-phase (two-year) tick–tock model that Intel adopted in 2006. The tick–tock model was no longer economically sustainable, according to Intel, because production of ever smaller dies becomes ever more costly.[1][2][3][4][5]

Wave[6] Process
(shrink)
ArchitectureOptimizations
1:
14 nm
2014:
Broadwell
(5th gen)
2015:
Skylake
(6th gen)
2016:
Kaby Lake
(7th gen)
2017:
Coffee Lake
(8th gen)
2018:
Coffee Lake Refresh
(9th gen)
2019:

Comet Lake

(10th gen)

References: [1][3][6][7]
2:
10 nm
2018:[note 1]
Cannon Lake
(8th gen, Palm Cove)
2019:
Ice Lake
(10th gen, Sunny Cove)
2020:
Tiger Lake
(11th gen, Willow Cove)
2021:
Alder Lake
(12th gen, Golden Cove)
References: [1][8][7]

Notes

  1. Cannon Lake: only 1 CPU released, microarchitecture dumped 1.5 year later.
gollark: <@331320482047721472> HelloBoi
gollark: This would also explain the RAM access memory.
gollark: Hmm, if it was a while ago it might be Opteron, i.e. bad, so I can mock it for its badness.
gollark: Is malbolgelisp concurrency?
gollark: How do they *have* that? Why are the RAM and CPU so weirdly balanced like that?

References

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