List of Xilinx FPGAs

This page contains general information about field-programmable gate array (FPGA) devices from Xilinx, based on official specifications.

Terminology

The fields in the table listed below describe the following:

  • Model – The marketing name for the device, assigned by Xilinx.
  • Launch – Date when the product was announced.
  • Sub-models – Some FPGA models have multiple sub-models.
  • Flip-Flops (K) – The number of flip-flops embedded within the FPGA fabric.
  • LUTs (K) – The number of lookup tables embedded within the FPGA fabric.
  • DSP Slices – The number of digital signal processor slices embedded within the FPGA fabric.
  • Peak DSP Performance (GMAC/s) – The maximum number of multiply-accumulate operations per second that can be performed by the digital signal processors that are embedded within the FPGA fabric. This is a theoretical best-case number.
  • PCIe – Bus by which the device is attached to an external system.
  • Max Distributed RAM (Mb) – Random Access Memory within the LUTs.[1]
  • Total Block RAM (Mb) – On-chip RAM that is not integrated within the LUTs.
  • UltraRAM (Mb) – An additional block of RAM that was introduced with the Zynq UltraScale+ FPGA line. UltraRAM can be powered down for extended periods of time.[2]

FPGAs with onboard CPUs

Zynq 7000-series[3]
  • Xilinx announced the Zynq 7000-series line in 2011[4]
  • All models are manufactured using a 28 nm fabrication process
  • Models have single or dual-core ARM Cortex-A9 CPUs
Model Launch Flip-Flops (K) LUTs (K) DSP

Slices

 Peak DSP

Performance

(GMAC/s)

 PCIe
Z-7010 2011[4] 35.2 17.6 80 100 -
Z-7015 92.4 46.2 160 200 Gen2 x4
Z-7020 2011[4] 106.4 53.2 220 276 -
Z-7030 2011[4] 157.2 78.6 400 593 Gen2 x4
Z-7035 343.8 171.9 900 1334 Gen2 x8
Z-7045 437.2 218.6 900 1334 Gen2 x8
Z-7100 2013[5] 554.8 277.4 2020 2622 Gen2 x8

Zynq UltraScale+[6]
  • Xilinx announced the Zynq UltraScale+ line in 2015[7]
  • All models are manufactured using a 16 nm fabrication process[8]
Model Launch Sub-models Flip-Flops

(K)

 LUTs (K) DSP

Slices

 PCIe Max

Distributed

RAM (Mb)

 Total

Block

RAM

(Mb)

 UltraRAM

(Mb)

ZU2 CG, EG 94 47 240 Gen2 x4 1.2 5.3 -
ZU3 CG, EG 141 71 360 Gen2 x4 1.8 7.6 -
ZU4 CG, EG, EV 176 88 728 Gen2 x4 2.6 4.5 13.5
ZU5 CG, EG, EV 234 117 1248 Gen2 x4 3.5 5.1 18
ZU6 CG, EG 429 215 1973 Gen2 x4 6.9 25.1 -
ZU7 CG, EG, EV 461 230 1728 Gen2 x4 6.2 11 27
ZU9 CG, EG 548 274 2520 Gen2 x4 8.8 32.1 -
ZU11 EG 597 299 2928 Gen2 x4 9.1 21.1 22.5
ZU15 EG 682 341 3528 Gen2 x4 11.3 26.2 31.5
ZU17 EG 847 423 1590 Gen2 x4 8 28 28.7
ZU19 EG 1045 523 1968 Gen2 x4 9.8 34.6 36

Sub-models of Zynq UltraScale+

Each model of Zynq UltraScale+ is available in up to 3 sub-models: CG, EG, and EV. The main differences among these sub-models are in the CPU and GPU configurations.[9]

CG EG EV
APU 2x Arm A53 4x Arm A53 4x Arm A53
RPU 2x Arm R5 2x Arm R5 2x Arm R5
GPU - Arm Mali-400MP2 Arm Mali-400MP2
VCU - - H.264/H.265

Versal

In 2018, Xilinx announced a product line called Versal.[10] Versal chips will contain CPU, GPU, DSP, and FPGA components. Versal will be fabricated using 7nm process technology. Xilinx has stated that Versal products will be available in the second half of 2019.[11]

FPGAs without onboard CPUs[12]
This list is incomplete; you can help by expanding it.

XC-series
Model Launch
XC2064 1985
XC3020 1988
XC4000 1991
XC3100 1992
XC3200 1992
XC5000 1994
XC8100 1995
XC6200 1995

Spartan
Model Launch
Spartan 1998
Spartan-II 2000
Spartan-3E 2005
Spartan-3A 2007
Spartan-6 2009
Spartan-7 2017

Virtex
Model Launch
Virtex 1998
Virtex-E 1999
Virtex-EM 2000
Virtex-II 2001
Virtex-IV 2005
Virtex-5 2006
Virtex-6 2009
Virtex-7 2010
Virtex UltraScale 2013[13]
Virtex UltraScale+ 2015[14]

Artix
Family Launch Process Logic cells Block RAM DSP slices MGT PCIe blocks Mem Intf BW IO pins VCCINT
nm Count (K) TITO (ns) TCKO (ns) Total (Mb) FMAX (MHz) Count Total GMAC/s FMAX (MHz) Type Count Gbps Total Gbps Type Count Type Gbps
Artix 7 2010 28 nm 16-215 0.94 0.4 0.9-13 509 45-740 929 628 GTP 0-16 6.6 211 x4 Gen2 1 DDR3 1066 106-500 1.00

Kintex
Family Launch Process Logic cells Block RAM UltraRAM DSP slices MGT PCIe blocks Mem Intf BW IO pins VCCINT
nm Count (K) TITO (ns) TCKO (ns) Total (Mb) FMAX (MHz) Total (Mb) FMAX (MHz) Count Total GMAC/s FMAX (MHz) Type Count Gbps Total Gbps Type Count Type Gbps
Kintex-7 2010 28 nm 66-478 0.58 0.26 5-34 601 240-1920 2845 741 GTX 4-32 12.5 800 x8 Gen2 1 DDR3 1866 285-500 1.00
Kintex UltraScale 2013[13] 20 nm 318-1451 12.7-75.9 660 768-5520 8180 741 GTH, GTY 12-64 16.3 2086 x8 Gen3 1-6 DDR3 2400 312-832 0.95
Kintex UltraScale+ 2015[14] 16 nm 356-1143 12.7-34.6 825 0-36 650 1368-3528 6287 891 GTH, GTY 16-76 32.75 3268 x16 Gen3 0-5 DDR4 2666 280-668 0.85
gollark: Really, it's your fault for being woken up by pings.
gollark: And/or they have different priorities to most other companies working on this stuff.
gollark: Their SoC design people are slightly ridiculously good, yes.
gollark: Or printers.
gollark: There are *time constraints* on *beard growth*? Oh no.

References
  1. Akthar, Shahul (2014-09-21). "Block RAM and Distributed RAM in Xilinx FPGA". All About FPGA. Retrieved 2018-12-03.
  2. "UltraRAM: Breakthrough Embedded Memory Integration on UltraScale+ Devices" (PDF). Xilinx. 2016-06-14. Retrieved 2018-12-03.
  3. "Zynq-7000 SoC Data Sheet: Overview" (PDF). Retrieved 2018-11-28.
  4. "Xilinx Introduces Zynq-7000 Family, Industry's First Extensible Processing Platform". PRNewsWire. 2011-03-01. Retrieved 2018-12-03.
  5. Maxfield, Clive. "Xilinx unveils new Zynq-7100 All Programmable SoCs". EE Times. Retrieved 2018-11-30.
  6. "Zynq UltraScale+ MPSoC Product Tables and Product Selection Guide" (PDF). Retrieved 2018-11-28.
  7. "Xilinx Ships Industry's First 16nm All Programmable MPSoC Ahead of Schedule". PRNewsWire. 2015-09-30. Retrieved 2018-12-03.
  8. "Zynq UltraScale+ MPSoC". Xilinx. Retrieved 2018-12-03.
  9. "UltraScale Architecture and Product Data Sheet: Overview" (PDF). Xilinx. Retrieved 2018-12-03.
  10. Merritt, Rick (2018-10-03). "Xilinx Unveils Versal SoC". EE Times Asia. Retrieved 2018-12-03.
  11. Leibson, Steven (2018-10-11). "Why does Xilinx say That its New 7nm Versal "ACAP" isn't an FPGA?". EE Journal. Retrieved 2018-12-03.
  12. Lazzaro, John. "Xilinx Part Family History". UC Berkeley. Retrieved 2018-12-03.
  13. "First 20nm UtraScale ASIC-Class FPGA From Xilinx". EE Times. 2013-07-09. Retrieved 2018-12-03.
  14. "Xilinx Unveils 16nm Ultrascale+ FPGAs, MPSoCs & 3D ICs". EE Times. 2015-02-24. Retrieved 2018-12-03.
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