How do general binaries take advantage from new instructionsets on new CPUs

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With every release of a new processor, there are changes to the instructionset the processor supports. For example, Haswell has Advanced Vector Extensions. However, when I run a program on a PC with a Haswell processor I usually run generic AMD64 binaries: the compiler doesn't know these instructions are available. How do these binaries still take advantage of the new instructions added in new architectures?

Martijn

Posted 2014-01-29T11:01:51.463

Reputation: 3 362

Answers

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Unless the binaries were complied to check for extensions and also to use them if they are present, they do not take advantage of new instructions from instruction set extensions.

Dan D.

Posted 2014-01-29T11:01:51.463

Reputation: 5 138

While on the one hand that sounds reasonable, it does lead to wonder why these new instructions are added if there is virtually no compiled software available for them. – Martijn – 2014-01-29T11:27:29.450

1There is software that exist but they are mainly single purpose tools – Ramhound – 2014-01-29T12:01:15.233

but really? All those instructions added to different processors since the 8086 in 1978 are not available to anyone downloading a blob compiled for x86? MMX, SSE1 to SSE5, AVX, all that stuff is not available to x86 compatible binaries? I can hardly believe that. – Martijn – 2014-01-29T13:06:55.697

Ugh, I apparently misread your answer, and binaries can be/are compiled to check for extensions? That is basically what my question comes down to. – Martijn – 2014-01-29T13:29:16.043

In addition, once the installed base of hardware supporting a given extension becomes sufficient, the extension can be assumed to be present (similar to OS, disk space, memory, or frequency requirements like "Windows _ or later"). Older hardware will generally produce illegal opcode exceptions (technically, a newer OS on old hardware could emulate such instructions to provide binary compatibility, but since most new instructions are added to improve performance emulation makes less sense [e.g., speech recognition at five words per hour by emulating AVX instructions on a Pentium MMX]). – Paul A. Clayton – 2014-01-29T17:35:11.753