Communication between CPU and Northbridge at different clock speeds?

0

I am interested in learning about how CPU's transfer data to peripherals, and came across the wikipedia article on FSB. While its probably a bit outdated compared to modern systems, my question still applies:

How does the CPU communicate with the Northbridge over the FSB when the CPU and FSB are using different clock speeds?

This can even be asked for all peripherals really - how does data transfer occur between them, when they are running at different clock speeds? Do they have something like a stall line that turns on when data is not ready?

marco9999

Posted 2016-11-03T16:34:01.303

Reputation: 3

Did you read any references which the article you refer to lists? – Run CMD – 2016-11-03T16:41:59.307

No, but I did try and search for something on the web, everything I came across was vauge. Nothing in the references helped either. – marco9999 – 2016-11-04T05:09:56.230

Answers

1

There are buffers between the CPU and other components. These buffer have one side that runs at the CPU speed and one side that runs at the device speed.

The CPU's write buffer is one example of such a buffer, typically adapting the CPU speed to the speed of its caches. Similar buffers adapt between the caches and main memory.

David Schwartz

Posted 2016-11-03T16:34:01.303

Reputation: 58 310

The buffer is typically just a register. – sawdust – 2016-11-03T18:57:10.293

@sawdust It depends which buffer you're talking about. The one between the CPU and its first-level cache is much more than just a register as it can complete writes out of order. – David Schwartz – 2016-11-03T19:01:35.597

Interesting. I was thinking the OP was more asking about bus protocols, being unaware of e.g. bus clock signals. – Run CMD – 2016-11-03T19:22:13.593

The bus protocols are pretty far from the CPU. I think the OP was imagining that the CPU would talk more or less directly to the bus, which is not at all true anymore. – David Schwartz – 2016-11-03T19:27:52.443

That definitely helps explain it. The wiki article also says the pipeline stalls if the write buffer is full, which I feel was the bit of info I was after. – marco9999 – 2016-11-04T05:21:39.687

Asked: 2016-11-03T16:34:01.303

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Active: 2016-11-03T17:06:15.193