The NAND flash chips have some built-in mechanisms to detect failures on write and erase operations, and will alert the controller if one fails. In this case, the controller can either try again, or treat that block as bad and map it out of its wear-leveling algorithm. Each page in the NAND device also has a spare area alongside the main data area, which is intended for metadata such as ECC and other forms of fault detection and tolerance. The controller can decide on its own fault tolerance scheme using the spare area. Hamming Codes are one common scheme, though there are several, including simple parity bits and Reed-Solomon codes. If things don't match up on a read operation, again, the controller is free to do as it pleases. Ideally, it would also map these blocks out of the wear leveling algorithm, and you would just lose capacity little by little until "too many" blocks fail, where "too many" depends on the algorithms and hardware structure sizes within the controller. Many first-cut controller designs simply declare an error to the operating system.
Note that this is not an MLC-specific issue; though MLC cells may be more prone to a read error, since there is necessarily a smaller margin for error, SLC cells fail with mostly the same mechanisms, and can be dealt with by the controller in the same way.