DDR5 SDRAM

DDR5 SDRAM is the official abbreviation for Double Data Rate 5 Synchronous Dynamic Random-Access Memory. Compared to its predecessor DDR4 SDRAM, DDR5 is planned to reduce power consumption, while doubling bandwidth.[2] The standard, originally targeted for 2018,[3] was released on 14 July 2020.[1]

This article is about DDR5 SDRAM. For graphics DDR5, based on DDR3, see GDDR5 SDRAM.

DDR5 SDRAM
Double Data Rate 5 Synchronous Dynamic Random-Access Memory

Type of RAM
Developer	JEDEC
Type	Synchronous dynamic random-access memory
Generation	5th generation
Release date	July 14, 2020 (2020-07-14) [1]
Voltage	1.1 V
Predecessor	DDR4 SDRAM

A new feature deemed Decision Feedback Equalization (DFE) enables IO speed scalability for higher bandwidth and performance improvement. DDR5 supports more bandwidth of its predecessor, DDR4 with 4.8 gigabits per second possible — but not shipping at launch.[4]

Rambus announced a working DDR5 DIMM in September 2017.[5][6] On November 15, 2018, SK Hynix announced completion of its first DDR5 RAM chip; it runs at 5200 MT/s at 1.1 volts.[7] In February 2019, SK Hynix announced a 6400 MT/s chip, the highest speed officially allowed by the preliminary DDR5 standard.[8] Some companies were planning to bring the first products to market by the end of 2019.[9]

The unrelated JEDEC standard LP-DDR5 (Low Power Double Data Rate 5), intended for laptops and smartphones, was released in February 2019.[10]

Compared to DDR4, DDR5 further reduces memory voltage to 1.1 V, thus reducing power consumption. DDR5 modules can incorporate on-board voltage regulators in order to reach higher speeds; as this will increase cost it is expected to be implemented only on server-grade and possibly high-end consumer modules.[6] DDR5 supports a speed of 51.2 GB/s per module[11] and 2 memory channels per module.[12][13]

There is a general expectation that most use-cases which currently use DDR4 will eventually migrate to DDR5. To be usable in desktops and servers (laptops will presumably use LPDDR5 instead), the integrated memory controllers of e.g. Intel's and AMD's CPUs will have to support it; as of June 2020, there has not been any official announcements of support from either, but a leaked slide shows planned DDR5 support on Intel's 2021 Sapphire Rapids microarchitecture.[14] According to AMD's Forrest Norrod, AMD's mid-2020 Zen 3 based third generation Epyc CPUs will still use DDR4.[15] A leaked internal AMD roadmap is reported to show DDR5 support for 2022 Zen 4 CPUs and Zen 3+ APUs.[16]

DIMMs versus memory chips

While previous SDRAM generations allowed unbuffered DIMMs which consisted of memory chips and passive wiring (plus a small serial presence detect ROM), DDR5 DIMMs require additional active circuitry, making the interface to the DIMM different from the interface to the RAM chips themselves.

First of all, a power supply; DDR5 DIMMs are supplied with 5V power,[17] and use on-board circuitry to convert to the lower voltage required by the memory chips. Final voltage regulation close to the point of use provides more stable power, and mirrors the development of voltage regulator modules for CPU power supplies.

Second, all DDR5 DIMMs are registered; a "registered clock driver" (RCD) chip converts a 7-bit-wide double data rate command/address bus to the DIMM to the 14-bit-wide single data rate command/address signals expected by the DRAM chips.

Third, there are two independent channels per DIMM. While earlier SDRAM generations had one CA bus controlling 64 or 72 (non-ECC/ECC) data lines, each DDR5 DIMM has two CA buses controlling 32 or 40 (non-ECC/ECC) data lines each, for a total of 64 or 80 data lines. A 4-byte bus width times a minimum burst length of 16 provides a minimum access size of 64 bytes, which matches the cache line size used by x86 microprocessors.

Operation

Standard DDR5 memory speeds range fom 4800 to 6400 million transfers per second (PC5-38400 to PC5-51200). Higher speeds may be added later, as happened with previous generations. Minimum burst length was doubled to 16, with the option of "burst chop" after 8 transfers.

Compared to DDR4 SDRAM, the number of bank groups is increased to 8, with the same 4 banks per group, for a total of 32.

Command encoding

DDR5 command encoding[18]

Command	CS	Command/addresss (CA) bits
		0	1	2	3	4	5	6	7	8	9	10	11	12	13
Active (activate): open a row	L	L	L	Row				Bank		Bank group			Chip
	H	Row													V
Unassigned, reserved	L	H	L	L	L	V
	H	V
Write pattern	L	H	L	L	H	L	H	Bank		Bank group			Chip
	H	V	Column								V	AP	H	V
Unassigned, reserved	L	H	L	L	H	H	V
	H	V
Mode register write	L	H	L	H	L	L	Address								V
	H	Data								V		CW	V
Mode register read	L	H	L	H	L	H	Address								V
	H	V										CW	V
Write	L	H	L	H	H	L	BL	Bank		Bank group			Chip
	H	V	Column								V	AP	WRP	V
Read	L	H	L	H	H	H	BL	Bank		Bank group			Chip
	H	V	Column								V	AP	V
Vref CA	L	H	H	L	L	L	Data								V
Refresh all	L	H	H	L	L	H	V					L	Chip
Refresh same bank	L	H	H	L	L	H	V	Bank		V		H	Chip
Precharge all	L	H	H	L	H	L	V					L	Chip
Precharge same bank	L	H	H	L	H	L	V	Bank		V		H	Chip
Precharge	L	H	H	L	H	H	V	Bank		Bank group			Chip
Unassigned, reserved	L	H	H	H	L	L	V
Self-refresh entry	L	H	H	H	L	H	V					L	V
Power-down entry	L	H	H	H	L	H	V					H	ODT	V
Multi-purpose command	L	H	H	H	H	L	Command								V
Power-down exit, No operation	L	H	H	H	H	H	V
Deselect (no operation)	H	X
Signal level H, high L, low V, valid, either low or high X, irrelevant Logic level      Active      Inactive      Not interpreted Control bits AP, Auto-precharge CW, Command word BL, Burst length ≠ 16 WRP, Write partial ODT, ODT remains enabled

The command encoding was significantly rearranged, and takes inspiration from that of LP-DDR4; commands are sent across a 14-bit bus, and while some simple commands take one cycle, any which include an address use two cycles to include 28 bits of information.

Also like LPDDR, the mode registers have been reduced to 8 bits each, while the number of them has been greatly increased.

References

1. Smith, Ryan (July 14, 2020). "DDR5 Memory Specification Released: Setting the Stage for DDR5-6400 And Beyond". AnandTech. Retrieved July 15, 2020.
2. Manion, Wayne (March 31, 2017). "DDR5 will boost bandwidth and lower power consumption". Tech Report. Retrieved April 1, 2017.
3. Cunningham, Andrew (March 31, 2017). "Next-generation DDR5 RAM will double the speed of DDR4 in 2018". Ars Technica. Retrieved January 15, 2018.
4. "New DDR5 SDRAM standard supports double the bandwidth of DDR4". AppleInsider. Retrieved July 21, 2020.
5. Lilly, Paul (September 22, 2017). "DDR5 memory is twice as fast as DDR4 and slated for 2019". PC Gamer. Retrieved January 15, 2018.
6. Tyson, Mark (September 22, 2017). "Rambus announces industry's first fully functional DDR5 DIMM - RAM - News". hexus.net.
7. Malakar, Abhishek (November 18, 2018). "SK Hynix Develops First 16 Gb DDR5-5200 Memory Chip". Archived from the original on March 31, 2019. Retrieved November 18, 2018.
8. Shilov, Anton. "SK Hynix Details DDR5-6400". www.anandtech.com.
9. "SK Hynix, Samsung Detail the DDR5 Products Arriving This Year". Tom's Hardware. February 23, 2019.
10. "JEDEC Updates Standard for Low Power Memory Devices: LPDDR5" (Press release). JEDEC. February 19, 2019.
11. Lilly, Paul (September 22, 2017). "DDR5 memory is twice as fast as DDR4 and slated for 2019".
12. "What We Know About DDR5 So Far". Tom's Hardware. June 7, 2019.
13. "DDR5 - The Definitive Guide!". April 27, 2019.
14. Verheyde 2019-05-22T16:50:03Z, Arne. "Leaked Intel Server Roadmap Shows DDR5, PCIe 5.0 in 2021, Granite Rapids in 2022". Tom's Hardware.
15. Cutress, Dr Ian. "An Interview with AMD's Forrest Norrod: Naples, Rome, Milan, & Genoa". www.anandtech.com.
16. "HW News - Supercomputer Cryptomining Malware, DDR5 & AMD, Ryzen 3 1200 AF". Gamers Nexus.
17. "P8900 PMIC for DDR5 RDIMMs and LRDIMMs". Renesas. Retrieved July 19, 2020.
    "P8911 PMIC for Client DDR5 Memory Modules". Renesas. Retrieved July 19, 2020.
18. "DDR5 Full Spec Draft Rev0.1" (PDF). JEDEC committee JC42.3. December 4, 2017. Retrieved July 19, 2020.

External links

• Main Memory: DDR4 & DDR5 SDRAM / JEDEC
• DDR5 Full Spec Draft Rev0.1 - Unfinished draft of the DDR5 standard.