Strain engineering

Strain engineering refers to a general strategy employed in semiconductor manufacturing to enhance device performance. Performance benefits are achieved by modulating strain in the transistor channel, which enhances electron mobility (or hole mobility) and thereby conductivity through the channel.

Strain engineering in CMOS manufacturing

The use of various strain engineering techniques has been reported by many prominent microprocessor manufacturers, including AMD, IBM, and Intel, primarily with regards to sub-130 nm technologies. One key consideration in using strain engineering in CMOS technologies is that PMOS and NMOS respond differently to different types of strain. Specifically, PMOS performance is best served by applying compressive strain to the channel, whereas NMOS receives benefit from tensile strain.[1] Many approaches to strain engineering induce strain locally, allowing both n-channel and p-channel strain to be modulated independently.

One prominent approach involves the use of a strain-inducing capping layer. CVD silicon nitride is a common choice for a strained capping layer, in that the magnitude and type of strain (e.g. tensile vs compressive) may be adjusted by modulating the deposition conditions, especially temperature.[2] Standard lithography patterning techniques can be used to selectively deposit strain-inducing capping layers, to deposit a compressive film over only the PMOS, for example.

Capping layers are key to the Dual Stress Liner (DSL) approach reported by IBM-AMD. In the DSL process, standard patterning and lithography techniques are used to selectively deposit a tensile silicon nitride film over the NMOS and a compressive silicon nitride film over the PMOS.

A second prominent approach involves the use of a silicon-rich solid solution, especially silicon-germanium, to modulate channel strain. One manufacturing method involves epitaxial growth of silicon on top of a relaxed silicon-germanium underlayer. Tensile strain is induced in the silicon as the lattice of the silicon layer is stretched to mimic the larger lattice constant of the underlying silicon-germanium. Conversely, compressive strain could be induced by using a solid solution with a smaller lattice constant, such as silicon-carbon. See, e.g., U.S. Patent No. 7,023,018. Another closely related method involves replacing the source and drain region of a MOSFET with silicon-germanium.[3]

Strain engineering in thin films

Epitaxial strain in thin films generally arises due to lattice mismatch between the film and its substrate, and can arise either during film growth or due to thermal expansion mismatch. Tuning this epitaxial strain can be used to moderate the properties of thin films and induce phase transitions. The misfit parameter (${\displaystyle f}$) is given by the equation below:[4]

${\displaystyle f=(a_{s}-a_{e})/a_{e}}$

where ${\displaystyle a_{e}}$ is the lattice parameter of the epitaxial film and ${\displaystyle a_{s}}$ is the lattice parameter of the substrate. After some critical film thickness, it becomes energetically favorable to relieve some mismatch strain through the formation of misfit dislocations or microtwins. Misfit dislocations can be interpreted as a dangling bond at an interface between layers with different lattice constants. This critical thickness (${\displaystyle h_{c}}$) was computed by Mathews and Blakeslee to be:

${\displaystyle h_{c}={\frac {b(2-\nu cos^{2}\alpha )[ln(h_{c}/b)+1]}{8\pi |f|(1+\nu )cos\lambda }}}$

where ${\displaystyle b}$ is the length of the Burgers vector, ${\displaystyle \nu }$ is the Poisson ratio, ${\displaystyle \alpha }$ is the angle between the Burgers vector and misfit dislocation line, and ${\displaystyle \lambda }$ is the angle between the Burgers vector and the vector normal to the dislocation's glide plane. The equilibrium in-plane strain for a thin film with a thickness (${\displaystyle h}$) that exceeds ${\displaystyle h_{c}}$ is then given by the expression:

${\displaystyle \epsilon _{||}={\frac {f}{|f|}}{\frac {b(1-\nu cos^{2}(\alpha )[ln(h/b)+1]}{8\pi |f|(1+\nu )cos\lambda }}}$

Strain relaxation at thin film interfaces via misfit dislocation nucleation and multiplication occurs in three stages which are distinguishable based on the relaxation rate. The first stage is dominated by glide of pre-existing dislocations and is characterized by a slow relaxation rate. The second stage has a faster relaxation rate, which depends on the mechanisms for dislocation nucleation in the material. Finally, the last stage represents a saturation in strain relaxation due to strain hardening.[5]

Strain engineering has been well-studied in complex oxide systems, in which epitaxial strain can strongly influence the coupling between the spin, charge, and orbital degrees of freedom, and thereby impact the electrical and magnetic properties. Epitaxial strain has been shown to induce metal-insulator transitions and shift the Curie temperature for the antiferromagnetic-to-ferromagnetic transition in ${\displaystyle {\ce {La_{1-x}Sr_{x}MnO_{3}}}}$.[6] In alloy thin films, epitaxial strain has been observed to impact the spinodal instability, and therefore impact the driving force for phase separation. This is explained as a coupling between the imposed epitaxial strain and the system’s composition-dependent elastic properties.[7] Researchers recently achieved very large strain in thick oxide films by incorporating nanowires/nanopillars in film matrix.[8] Additionally, in two dimensional materials such as WSe
₂ strain has been shown to induce conversion from an indirect semiconductor to a direct semiconductor allowing a hundred-fold increase in the light emission rate.[9]

Strain engineering in phase-change memory

Bi-axial strain has been used to reduce the switching energy in interfacial phase-change memory (iPCM) materials. Phase-change memory materials have been commercially used in non-volatile memory cells.[10] Interfacial phase change materials are a superlattice of Sb2Te3 and GeTe.[11] The average superlattice composition can be Ge2Sb2Te5, which is a well studied phase change alloy. There is a large change in the materials electrical resistance when atoms at the interface diffussively disorder.[12] In contrast to the Ge2Sb2Te5 alloy, which needs to amorphise to switch, the strained iPCM materials partially disorder at the interface.[12] When the GeTe layers are bi-axially strained, there is more room for atomic transitions and the activation energy for switching is lowered. And when these materials are included in phase-change memory devices, the switching energy lowered, the switching voltage is lowered, and the switching time is shortened.[13] In short strain considerably improves the memory cell performance.

See also

• Strained silicon

References

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2. Martyniuk, M, Antoszewski, J. Musca, C.A., Dell, J.M., Faraone, L. Smart Mater. Struct. 15 (2006) S29-S38)
3. Weiss, Peter (28 February 2004). "Straining for Speed". Science News Online. Archived from the original on 12 September 2005.
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5. Zhmakin, A. I. (2011). "Strain relaxation models". arXiv:1102.5000 [cond-mat.mtrl-sci].
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9. Wu, Wei; Wang, Jin; Ercius, Peter; Wright, Nicomario; Leppert-Simenauer, Danielle; Burke, Robert; Dubey, Madan; Dongare, Avinash; Pettes, Michael (2018). "Giant Mechano-Optoelectronic Effect in an Atomically Thin Semiconductor" (PDF). Nano Letters. 18 (4): 2351–2357. Bibcode:2018NanoL..18.2351W. doi:10.1021/acs.nanolett.7b05229. PMID 29558623.
10. Micron. "Micron Announces Availability of Phase-Change Memory for Mobile Devices". Micron. Retrieved 26 February 2018.
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