Lotzwil railway station

Lotzwil railway station (German: Bahnhof Lotzwil) is a railway station in the municipality of Lotzwil, in the Swiss canton of Bern. It is an intermediate stop on the standard gauge Langenthal–Huttwil line of BLS AG.

Lotzwil
The station building in 2018
LocationLotzwil
Switzerland
Coordinates47°11′20″N 7°47′17″E
Owned byBLS AG
Line(s)Langenthal–Huttwil line
Train operatorsBLS AG
Services
Preceding station Lucerne S-Bahn Following station
Langenthal Süd
towards Langenthal
S6 Gutenburg
towards Lucerne
S7 Gutenburg
towards Wolhusen
Location
Lotzwil
Location within Switzerland
Lotzwil
Lotzwil (Canton of Bern)

Services

The following services stop at Lotzwil:[1]

gollark: The rest of the instruction consists of variable-width (for fun) target specifiers. The first N target specifiers in an operation are used as destinations and the remaining ones as sources. N varies per opcode. They can be of the form `000DDD` (pop/push from/to stack index DDD), `001EEE` (peek stack index EEE if source, if destination then push onto EEE if it is empty), `010FFFFFFFF` (8-bit immediate value FFFFFFFF; writes are discarded), `011GGGGGGGGGGGGGGGG` (16-bit immediate value GGGGGGGGGGGGGGGG; writes are also discarded), `100[H 31 times]` (31-bit immediate because bee you), `101IIIIIIIIIIIIIIII` (16 bits of memory location relative to the base memory address register of the stack the operation is conditional on), `110JJJJJJJJJJJJJJJJ` (16 bit memory location relative to the top value on that stack instead), `1111LLLMMM` (memory address equal to base memory address of stack LLL plus top of stack MMM), or `1110NNN` (base memory address register of stack MMM).Opcodes (numbered from 0 in order): MOV (1 source, as many destinations as can be parsed validly; the value is copied to all of them), ADD (1 destination, multiple sources), JMP (1 source), NOT (same as MOV), WR (write to output port; multiple sources, first is port number), RE (read from input port; one source for port number, multiple destinations), SUB, AND, OR, XOR, SHR, SHL (bitwise operations), MUL, ROR, ROL, NOP, MUL2 (multiplication with two outputs).
gollark: osmarksISA™️-2028 is a VLIW stack machine. Specifically, it executes a 384-bit instruction composed of 8 48-bit operations in parallel. There are 8 stacks, for safety. Each stack also has an associated base memory address register, which is used in some "addressing modes". Each stack holds 64-bit integers; popping/peeking an empty stack simply returns 0, and the stacks can hold at most 32 items. Exceeding a stack's capacity is runtime undefined behaviour. The operation encoding is: `AABBBCCCCCCCCC`:A = 2-bit conditional operation mode - 0 is "run unconditionally", 1 is "run if top value on stack is 0", 2 is "run if not 0", 3 is "run if first bit is ~~negative~~ 1".B = 3-bit index for the stack to use for the conditional.C = 9-bit opcode (for extensibility).
gollark: By "really fast", I mean "in a few decaminutes, probably".
gollark: I suppose I could just specify it really fast.
gollark: I could, but do I really want to?

References

  1. "Langenthal - Wolhusen - Luzern" (PDF) (in German). Bundesamt für Verkehr. 21 October 2019. Retrieved 22 June 2020.
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