IBM zEC12 (microprocessor)
The zEC12 microprocessor (zEnterprise EC12 or just z12) is a chip made by IBM for their zEnterprise EC12 and zEnterprise BC12 mainframe computers, announced on August 28, 2012. It is manufactured at the East Fishkill, New York fabrication plant (previously owned by IBM but production will continue for ten years by new owner GlobalFoundries). The processor began shipping in the fall of 2012. IBM stated that it was the world's fastest microprocessor and is about 25% faster than its predecessor the z196.[1][2]
| General Info | |
|---|---|
| Launched | 2012 |
| Designed by | IBM |
| Performance | |
| Max. CPU clock rate | 5.5 GHz |
| Cache | |
| L1 cache | 64+96 KB/core |
| L2 cache | 1+1 MB/core |
| L3 cache | 48 MB/chip |
| Architecture and classification | |
| Min. feature size | 32 nm |
| Instruction set | z/Architecture (ARCHLVL 3) |
| Physical specifications | |
| Cores |
|
| History | |
| Predecessor | z196 |
| Successor | z13 |
Description
The chip measures 597.24 mm2 and consists of 2.75 billion transistors fabricated in IBM's 32 nm CMOS silicon on insulator fabrication process, supporting speeds of 5.5 GHz, the highest clock speed CPU ever produced for commercial sale.[3]
The processor implements the CISC z/Architecture with a superscalar, out-of-order pipeline and some new instructions mainly related to transactional execution. The cores have numerous other enhancements such as better branch prediction, out of order execution and one dedicated co-processor for compression and cryptography. The instruction pipeline has 15 to 17 stages; the instruction queue can hold 40 instructions; and up to 90 instructions can be "in flight". It has six cores, each with a private 64 KB L1 instruction cache, a private 96 KB L1 data cache, a private 1 MB L2 cache instruction cache, and a private 1 MB L2 data cache. In addition, there is a 48 MB shared L3 cache implemented in eDRAM and controlled by two on-chip L3 cache controllers. There's also an additional shared L1 cache used for compression and cryptography operations.
Each core has six RISC-like execution units, including two integer units, two load-store units, one binary floating point unit and one decimal floating point unit. The zEC12 chip can decode three instructions and execute seven operations in a single clock cycle.[4] Attached to each core is a special co-processor accelerator unit; in the previous z CPU there were two shared by all four cores.
The zEC12 chip has on board multi-channel DDR3 RAM memory controller supporting a RAID like configuration to recover from memory faults. The zEC12 also includes two GX bus controllers for accessing host channel adapters and peripherals.
Shared Cache
Even though each chip has 48 MB L3 cache shared by the 6 cores and other on-die facilities for symmetric multiprocessing (SMP), there are 2 dedicated companion chips called the Shared Cache (SC) that each adds 192 MB off-die L4 cache for a total of 384 MB L4 cache. L4 cache is shared by all processors in the book. The SC chips are manufactured on the same process as the zEC12 processor chips, measures 28.4 x 23.9 mm and have 3.3 billion transistors each.[4]
Multi-chip module
The zEnterprise System EC12 uses multi-chip modules (MCMs) which allows for six zEC12 chips to be on a single module. Each MCM has two shared cache chips allowing processors on the MCM to be connected with 40 GB/s links. One zEC12 chip draws in the region of 300 W and the MCM is cooled by a liquid cooling mechanism capable of 1800 W.[4]
The different models of the zEnterprise System have a different number of active cores. To accomplish this, some processors in each MCM may have its fifth and/or sixth core disabled.
See also
- z/Architecture
- IBM System z
- Mainframe computer