Floating body effect

The floating body effect is the effect of dependence of the body potential of a transistor realized by the silicon on insulator (SOI) technology on the history of its biasing and the carrier recombination processes. The transistor's body forms a capacitor against the insulated substrate. The charge accumulates on this capacitor and may cause adverse effects, for example, opening of parasitic transistors in the structure and causing off-state leakages, resulting in higher current consumption and in case of DRAM in loss of information from the memory cells. It also causes the history effect, the dependence of the threshold voltage of the transistor on its previous states. In analog devices, the floating body effect is known as the kink effect.

One countermeasure to floating body effect involves use of fully depleted devices. The insulator layer in FD devices is significantly thinner than the channel depletion width. The charge and thus also the body potential of the transistors is therefore fixed.[1] However, the short-channel effect is worsened in the FD devices, the body may still charge up if both source and drain are high, and the architecture is unsuitable for some analog devices that require contact with the body.[2] Hybrid trench isolation is another approach.[3]

While floating body effect presents a problem in SOI DRAM chips, it is exploited as the underlying principle for Z-RAM and T-RAM technologies. For this reason, the effect is sometimes called the Cinderella effect in the context of these technologies, because it transforms a disadvantage into an advantage.[4] AMD and Hynix licensed Z-RAM, but as of 2008 had not put it into production.[5] Another similar technology (and Z-RAM competitor) developed at Toshiba[6][7] and refined at Intel is Floating Body Cell (FBC).[8][5]

References
  1. Shahidi, G. G. (2002). "SOI technology for the GHz era". IBM Journal of Research and Development. IBM. 46 (2.3): 121–131. doi:10.1147/rd.462.0121. ISSN 0018-8646.
  2. Cataldo, Anthony (2001-11-26). "Intel Does About-Face on SOI, Backs High-k Dielectric". EE Times. Stanford, California. Retrieved 2019-03-30.
  3. Kallender, Paul (2001-12-17). "Mitsubishi SOI Process Uses Hybrid Trench Isolation". EE Times. Makuhari, Japan. Retrieved 2019-03-30.
  4. Z-RAM Shirnks Embedded Memory, Microprocessor Report
  5. Mark LaPedus (17 Jun 2008). "Intel explores floating-body cells on SOI". EE Times. Retrieved 23 May 2019.
  6. Samuel K. Moore (1 Jan 2007). "Winner: Masters of Memory Swiss firm crams 5 megabytes of RAM into the space of one". IEEE Spectrum. Retrieved 23 Mar 2019.
  7. Yoshiko Hara (7 Feb 2002). "Toshiba cuts capacitor from DRAM cell design". EE Times. Retrieved 23 Mar 2019.
  8. Nick Farrell (11 Dec 2006). "Intel talks up Floating Body Cells". The Inquirer. Retrieved 23 Mar 2019.

Further reading
  • Takashi Ohsawa; Takeshi Hamamoto (2011). Floating Body Cell: A Novel Capacitor-Less DRAM Cell. Pan Stanford Publishing. ISBN 978-981-4303-07-1.


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