What are functional unit and control logic of a cpu?

Question

From the book Modern Operating systems;

The abundance of transistors on a single chip is leading to a problem: what to do with all of them?

We saw one approach above: superscalar architectures, with multiple functional units. But as the number of transistors increases, even more is possible. One obvious thing to do is put bigger caches on the CPU chip. That is definitely hap- pening, but eventually the point of diminishing returns will be reached.

The obvious next step is to replicate not only the functional units, but also some of the control logic. The Intel Pentium 4 introduced this property, called multithreading or hyperthreading (Intel’s name for it), to the x86 processor, and several other CPU chips also have it—including the SPARC, the Power5, the Intel Xeon, and the Intel Core family. To a first approximation, what it does is allow the CPU to hold the state of two different threads and then switch back and forth on a nanosecond time scale. (A thread is a kind of lightweight process, which, in turn, is a running program; we will get into the details in Chap. 2.)

A superscalar architecture is given in a previous figure 1-7(b):

I wonder what a functional unit and a control logic in a cpu mean?

Does a superscalar architecture also replicate control logic?

Are "functional unit" and "Execute unit" the same thing?

Is "control logic" the same as "Fetch unit" and "Decode unit"?

I am hesitant to answer yes to the above questions because of the following reasons. The text says superscalar architectures replicate the functional units, while multithreading replicates not only the functional units, but also the control logic.

• But in figure 1.7(b), the superscalar one have multiple fetch and decode units besides multiple execute units, so I am not sure if "control logic == fetch and decode units" and "functional unit == execute unit".

• Also by multithreading, the text actually means time-multiplex. I don't know how replicating control logic is necessary for time-multiplex? Can't multiple threads or processes share the same control units (fetch unit and decode unit) at different times?

Answer 1

Are "functional unit" and "Execute unit" the same thing?

Yes (in the context of how they are used in your book).

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Execution unit

In computer engineering, an execution unit (also called a functional unit) is a part of a CPU that performs the operations and calculations called for by the computer program. It may have its own internal control sequence unit (not to be confused with the CPUs main control unit), some registers, and other internal units such as a sub-ALU or FPU, or some smaller, more specific components.[1]

It is common for modern CPUs to have multiple parallel execution units, referred to as scalar or superscalar design. The simplest arrangement is to use one, the bus manager, to manage the memory interface, and the others to perform calculations. Additionally, modern CPUs' execution units are usually pipelined.

Source Execution unit

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Is "control logic" the same as "Fetch unit" and "Decode unit"?

Yes (in the context of how they are used in your book).

The control unit is a component of a computer's central processing unit (CPU) that directs operation of the processor. It tells the computer's memory, arithmetic/logic unit and input and output devices how to respond to a program's instructions.

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The Control Unit (CU) is generally a sizable collection of complex digital circuitry interconnecting and controlling the many execution units contained within a CPU.[citation needed] The CU is normally the first CPU unit to accept from an externally stored computer program, a single instruction, based on the CPU’s instruction set, then decode this individual instruction into several sequential steps (fetching addresses/data from registers/memory, managing execution [i.e. data sent to the ALU or I/O], and storing the resulting data back into registers/memory) that controls and coordinates the CPU’s interworks.

Source Control unit

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Central processing unit

Fetch

The first step, fetch, involves retrieving an instruction (which is represented by a number or sequence of numbers) from program memory. The instruction's location (address) in program memory is determined by a program counter (PC), which stores a number that identifies the address of the next instruction to be fetched. After an instruction is fetched, the PC is incremented by the length of the instruction so that it will contain the address of the next instruction in the sequence.[d] Often, the instruction to be fetched must be retrieved from relatively slow memory, causing the CPU to stall while waiting for the instruction to be returned. This issue is largely addressed in modern processors by caches and pipeline architectures (see below).

Decode

The instruction that the CPU fetches from memory determines what the CPU has to do. In the decode step, the instruction is broken up into parts that have significance to other portions of the CPU. The way in which the numerical instruction value is interpreted is defined by the CPU's instruction set architecture (ISA).[e] Often, one group of numbers in the instruction, called the opcode, indicates which operation to perform. The remaining parts of the number usually provide information required for that instruction, such as operands for an addition operation. Such operands may be given as a constant value (called an immediate value), or as a place to locate a value: a register or a memory address, as determined by some addressing mode.

In some CPU designs the instruction decoder is implemented as a hardwired, unchangeable circuit. In others, a microprogram is used to translate instructions into sets of CPU configuration signals that are applied sequentially over multiple clock pulses. In some cases the memory that stores the microprogram is rewritable, making it possible to change the way in which the CPU decodes instructions.

Source Central processing unit

Answer 2

Functional units of CPU

1. Information from RAM sent along BIU which makes a copy and sends it to L2 cache.

2. BIU determines if the information is data or instruction. and sends it to appropriate L1 cache.

3. CU fetches instruction from instruction cache breaks it down into micro instructions before delivering to execution unit.

4. Execution unit consists of ALU, FPU or MMX (graphics/audio) It checks if data is needed, fetches data from L1 data cache → L2 cache → RAM.