Why is PCI-E speed so fast?

Question

The wiki page for PCI-E says it is x16 bandwidth is 31.508 GB/s. Why is it so fast? Does it talk with CPU directly?

Answer 1

A good explanation can be found on the Wiki page itself here:

A key difference between PCIe and earlier buses is a topology based on point-to-point serial links, rather than a shared parallel bus architecture.

As well as here:

Conceptually, the PCIe bus can be thought of as a high-speed serial replacement of the older (parallel) PCI/PCI-X bus.

And further explained here; emphasis mine on the key issue with regards to parallel communications in the standard PCI architecture:

The bonded serial format was chosen over a traditional parallel bus format due to the latter's inherent limitations, including single-duplex operation, excess signal count and an inherently lower bandwidth due to timing skew. Timing skew results from separate electrical signals within a parallel interface traveling down different-length conductors, on potentially different printed circuit board layers, at possibly different signal velocities. Despite being transmitted simultaneously as a single word, signals on a parallel interface experience different travel times and arrive at their destinations at different moments. When the interface clock rate is increased to a point where its inverse (i.e., its clock period) is shorter than the largest possible time between signal arrivals, the signals no longer arrive with sufficient coincidence to make recovery of the transmitted word possible. Since timing skew over a parallel bus can amount to a few nanoseconds, the resulting bandwidth limitation is in the range of hundreds of megahertz.

And even more details in this article on PCI SSD’s and why they are so much more faster that SATA SSD’s. Specifically this chart I am embedding:

Note the line in that reads, “Many CPUs have built in PCIe.” Which basically translates into a direct channel between the CPU and the PCIe bus. And what is that PCH Chipset about? More Wiki details; again emphasis is mine:

The PCH controls certain data paths and support functions used in conjunction with Intel CPUs. These include clocking (the system clock), Flexible Display Interface (FDI) and Direct Media Interface (DMI), although FDI is only used when the chipset is required to support a processor with integrated graphics. As such, I/O functions are reassigned between this new central hub and the CPU compared to the previous architecture: some northbridge functions, the memory controller and PCI-e lanes, were integrated into the CPU while the PCH took over the remaining functions in addition to the traditional roles of the southbridge.

So that is basically it: PCI parallel communications and it’s inherent limits versus PCIe serial communications—coupled with the built in PCIe support in many CPUs have which allows them to skip having to use the platform controller hub—allows PCIe to overcome those older systems PCI architecture limits. Additionally, the point-to-point topology of the overall PCIe architecture related to connections to other PCIe devices on the host machine itself allows for smoother communications between those PCIe devices.