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What is the topology of the interconnection network within an Intel core i7, i3 or i5 processor? Is it using a:
- Crossbar
- Ring
- Hypercube
- Mesh
- Butterfly
- or something else?
rose
Posted 2014-04-11T17:03:54.347
Reputation: 117
What is the on-chip network topology of an Intel Core i7 (or i3 or i5) processor?
Answers
3
Quoting from Wikipedia:
Intel Core i7 as an Intel brand name applies to several families of desktop and laptop 64-bit x86-64 processors using the Nehalem, Westmere, Sandy Bridge, Ivy Bridge and Haswell microarchitectures.
Given such a long history, it is not especially surprising that more than one interconnect topology has been used. According to David Kanter's article on Sandy Bridge, Nehalem and Westmere used a crossbar interconnect, while Sandy Bridge used a ring interconnect with four different rings: "request, snoop, acknowledge and a 32B wide data ring".
As David Kanter's article points out, using a ring interconnect makes flexibility in the number of interconnect nodes easier than if a crossbar was used.
According to page 6 of the 2012 IDF presentation "Technology Insight: Intel Next Generation Microarchitecture Code Name Haswell", Haswell retains the ring interconnect of Sandy Bridge and Ivy Bridge.
Paul A. Clayton
Posted 2014-04-11T17:03:54.347
Reputation: 1 153
2
It's known as Intel QuickPath Interconnect (QPI). You can read Intel's whitepaper about it here.
They describe it as "point to point" which is also how a mesh topology is described.
Jason
Posted 2014-04-11T17:03:54.347
Reputation: 5 925
The question was asking about topology not protocol. – Paul A. Clayton – 2014-04-11T22:35:58.697
@PaulA.Clayton Not my forte, but figure 6 appears to show the topology. Intel describes it as "point to point", which is the same as the definition for a mesh topology. I'll add this to the answer. – Jason – 2014-04-11T23:11:38.497
Since the OP was asking about Core i7, i3, i5, presumably he is not concerned with the off-chip (Xeon DP/MP) interconnect. With Xeon DP only two sockets are supported, so topology is somewhat moot. I seem to recall Xeon MP has three coherent QPI links, so a 3 socket system could have all-to-all, but a four socket system would look like a square with diagonal crossings (which provides more direct connections than a 2D-cube [which is the same as a 4 node mesh and a 4 node bidirectional ring]). – Paul A. Clayton – 2014-04-11T23:32:59.860