What does PCI (not PCI-E) bus speed of 66MHz really mean?

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According to this article , the bus is the circuit that connects the motherboard . The faster the speed of the bus , the quicker data can be transferred . Bus speed is measured in MHz (Mega Hertz) and a bus speed of 66 MHZ means that that are 66 million cycles per second . Hertz means how the frequency of x every second

For CPU , 66 MHz means 66 million instructions can be processed every second

How about for Bus ?? How much data is terms of btyes is transferred for every cycle ??

Computernerd

Posted 2014-03-12T17:42:49.103

Reputation: 837

"For CPU , 66 MHz means 66 million instructions can be processed every second" -- That's an incorrect assumption, more than one instruction can be performed per clock cycle. As for your question, the size of the bus matters. IE: a 32-bit data bus can move less data at once than a 64-bit data bus could. – Ƭᴇcʜιᴇ007 – 2014-03-12T17:48:21.830

When it comes to frequency considerations, there are other factors to be considered... Such as bus widths. Simply, a pin can change state 66 million times in a second at (66 MHz). – Ghassan – 2014-03-12T17:51:20.920

For the amount of data (in bytes) being sent, it depends on how big the bus is (in bits). If you have a 32-bit bus, you can send 4 Bytes of information per cycle (8 bits / 1 byte). – None – 2014-03-12T17:52:54.047

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To continue on what @techie007 said, it is not limited to more than one CPU instuction per cycle. DDR Memory will do two data transfers per one clock cycle.

– Scott Chamberlain – 2014-03-12T18:22:55.403

Answers

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It's the speed at which the PCI protocol operates over the bus. It's the CLK signal in the illustration below.

Wikipedia gives this formula for 32-bit 33MHz PCI, which is x2 for 32-bit 64MHz PCI:

Peak transfer rate of 133 MB/s (133 megabytes per second) for 32-bit bus width (33.33 MHz × 32 bits ÷ 8 bits/byte = 133 MB/s)

There is an address phase and a data phase in the protocol as you can see below, so not all of the 266MBytes/sec will be dedicated to actual work. There is a bit of overhead.

From this:

The basic transfer mechanism is a burst, composed of an address phase and one or more data phases.

Typical read and write transfers are illustrated below:

enter image description here

This article mentions an effective throughput of 90MBytes/sec of the theoretical 133MBytes/sec due to the overhead. For 32-bit 66MHz it would be doubled.

LawrenceC

Posted 2014-03-12T17:42:49.103

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