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Firstly, this is true, right? I feel that reads will always be faster than writes, also this guy here does some experiments to "prove" it. He doesn't explain why, just mentions "caching issues". (and his experiments don't seem to worry about prefetching)
But I don't understand why. If it matters, let's assume we're talking about the Nehalem architecture (like i7) which has L1, L2 cache for each core and then a shared inclusive L3 cache.
Probably this is because I don't correctly understand how reads and writes work, so I'll write my understanding. Please tell me if something is wrong.
If I read some memory, following steps should happen: (assume all cache misses)
1. Check if already in L1 cache, miss
2. Check if in L2 cache, miss
3. Check if in L3 cache, miss
4. Fetch from memory into (L1?) cache
Not sure about last step. Does data percolate down caches, meaning that in case of cache miss memory is read into L3/L2/L1 first and then read from there? Or can it "bypass" all caches and then caching happens in parallel for later. (reading = access all caches + fetch from RAM to cache + read from cache?)
Then write:
1. All caches have to be checked (read) in this case too
2. If there's a hit, write there and since Nehalem has write through caches,
write to memory immediately and in parallel
3. If all caches miss, write to memory directly?
Again not sure about last step. Can write be done "bypassing" all caches or writing involves always reading into the cache first, modifying the cached copy and letting the write-through hardware actually write to memory location in RAM? (writing = read all caches + fetch from RAM to cache + write to cache, written to RAM in parallel ==> writing is almost a superset of reading?)
2Please don't cross-post between SE sites. Either flag a mod to request and/or wait for a mod to migrate your other question here. If you want it here and not there, since you've already posted both places, please consider going and deleting it from SO. – Ƭᴇcʜιᴇ007 – 2013-11-12T20:02:08.857
1Reading something is passive, writing (changing) something is active. Activity is almost always harder than passivity. ;) – Ƭᴇcʜιᴇ007 – 2013-11-12T20:17:09.540
http://electronics.stackexchange.com/questions/17549/i-know-why-dram-is-slower-to-write-than-to-read-but-why-is-the-l1-l2-cache-ra – Ƭᴇcʜιᴇ007 – 2013-11-12T20:17:48.697
@user2898278 - Do you have any possible sources more reliable then a random blog? – Ramhound – 2013-11-12T20:23:26.227
You have got something elementary wrong here. Every bit of data is addressed...there's no trickling down cache levels looking for data as if you were guessing. – M.Bennett – 2013-11-12T21:15:47.463
@techie007, thank you for your response. I'll remove it from SO. As I said, I intuitively understand why "pure write" should be somewhat slower than a "pure read" and had read that electronics thread before posting this, but I want to know about "actual" read and write times including all effects due to caching, not just moving data from RAM to/from cache ("pure" read/write). – user2898278 – 2013-11-12T21:44:13.723
@Ramhound, I also tested this with a tool called lmbench. I got write speeds consistently slower than read speeds by about 1.5 times. Although I'm not sure about the accuracy of the program on modern processors. But data is actually all over the internet suggesting that write is much slower, like this. But there is also some data that suggests otherwise, so I don't know what's happening.see
– user2898278 – 2013-11-12T21:59:36.183@M.Bennett, Every bit is addressable inside the RAM, of course, but reads and writes are done in multiples of cache line size from the RAM. When you say "every bit is addressed", do you mean the same thing as "bypassing caches" as I wrote in my question? I'm not sure if the CPU can read/write directly from/to the memory in any situation or these operations must go through the cache (in the former case, there would be separate physical connection b/w RAM and processor I think, is that the case?) – user2898278 – 2013-11-12T22:09:14.703
Add your data to your question please. – Ramhound – 2013-11-12T22:51:47.610
@user2898278 This isn't a discussion forum. If you want to discuss this at length, you'll probably be better off hitting the chat, or an actual discussion forum.
– Ƭᴇcʜιᴇ007 – 2013-11-12T23:32:07.263