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I'm an absolute beginner starting to understand the PCI Express protocol and I need some clarifications about its mechanics.
I understood that a PCI Express endpoint device may have some memory BAR mapped in the system memory (is it always RAM the system memory we are talking about?). I need to understand what happens when I send from the CPU to the device (A) a memory read request, addressing a certain memory address (first memory BAR, offset 0).
Let's assume that my device doesn't have any in-device memory.
The root complex on behalf of CPU creates the TLP and forwards it to device (A) because the memory address of destination is assigned to (A).
A receives the TLP, unpacks it, and creates a completion TLP containing data coming from its internal application logic.
Now the TLP travels backwards to the Root Complex that unpacks it, gathers the interesting data and gives it back to the the CPU.
What is the system memory role during this communication? None?
Does the root complex communicate (in this case) with the physical memory of the system, other than sending and receiving packets to/from the endpoint?
To some people it may seem a silly question but for me this is crucial to understand the connection between the physical memory and the memory address BARs assigned to each PCI Express device.
What does BAR stand for? – None – 2013-06-13T10:57:46.490
1Base Address Register. – LawrenceC – 2013-06-13T11:38:02.687
Thank you very much Hennes, I really need to understand if the physical memory addressed by the memory BARs of a PCIe device resides in the device itself, is it part of the RAM, both, none? When we refer to memory as a whole, is it the sum of RAM + devices memories? the answer ultrasawblade gave seems to go in that direction, but I'm not sure – Jacopo Reggiani – 2013-06-13T16:11:26.957
"Memory as whole" in the way you are saying is simply a range of addresses. A better term is "CPU address space." When the CPU issues a
MOV
instruction to read or write from an address, it can be set up where things other than RAM respond. This was quite common on older systems, and I believe most ARM-based CPU's still mostly rely entirely on I/O devices appearing like and being addressable in the same way as RAM. – LawrenceC – 2013-06-14T16:33:09.420