How to optimize PLL voltage

I am overclocking my Core i7 (Ivy Bridge 3770K), aiming for a moderate overclock.
Currently I have it easily stable at a pleasant 4.4GHZ - BCLK defaulted at 100.00MHz, with the multiplier set to x44.

While it is currently stable (tested using Prime95 torture test for a few hours), it does generate some more heat than I would optimally like. Nowhere near overheating, but still requiring the fan to run a bit loud.

I read in this article on Overclock.net, and verified with more experienced overclockers, that lowering the PLL voltage in the UEFI should lower the temperature a little bit.

So, how much should I try to lower it? Just keep going iteratively, as long as it is still stable, or stop arbitrarily at 1.500v (as that article indicates)?
How much could I typically expect to lower the temperature? So far it seems I might have lowered it 2-3C, but its hard to tell since that is less than the fluctuations in ambient temperature.
Most importantly, What exactly does the PLL voltage setting even do? I would feel a lot more comfortable managing this setting manually, if I understood its function. I haven't found anywhere a better explanation of it's responsibilities in the system, other than explaining what a PLL is.

(My motherboard is a GA-Z77-D3H, if it matters...)

AviD

Posted 2013-04-15T13:43:22.753

Reputation: 481

Answers

The PLL voltage setting determines the voltage fed to the CPU's phase locked loop section. The phase locked loop section generates the clock signals for different parts of the CPU that are clocked at different frequencies. It generates the main core clock, the video clock (if the CPU has a video controller), the memory controller clock, the bus clocks, and so on.

The PLL is designed to run at a voltage of 1.8V and exceeding 1.98V is dangerous. However, when overclocking, stability seems to be better for many people in the 1.5V to 1.7V range. The only way it would reduce temperature significantly was if it allowed you to drop the core voltage.

David Schwartz

Posted 2013-04-15T13:43:22.753

Reputation: 58 310

Thank you, so the PLL is responsible for the timing of the BCLK? What effect does more/less voltage have on that? – AviD – 2013-04-15T14:15:42.757

Re heat - you're saying not to bother with lowering the PLL voltage for the purpose of reducing heat, instead just lower it enough for stability and leave it alone? Better at the top or the bottom of that range? – AviD – 2013-04-15T14:16:57.140

1@AviD: The PLL is responsible for generating the BCLK, yes. More or less voltage might effect how good a job it does of generating clean, stable clocks. It also effects how stable it can keep the clock when the multiplier is changed. And yes, if you're going to mess with it, you can lower it for stability. If that lets you lower the core voltage, then that will help with heat. I would never suggest raising it except for extreme overclocking with extreme cooling. (It might need more voltage to be able to generate very high clock speeds above its design range.) – David Schwartz – 2013-04-15T14:20:38.270

Thanks David! I think this might be exactly what I am looking for - I will test this out. I did not see mentioned anywhere that the point of lowering the PLL (besides stability) is that it also affects the stable range of Vcore (I've already lowered that as much as stabley possible, down to 1.200v). Can you explain why/how the PLL affects Vcore? – AviD – 2013-04-15T14:27:02.970

Just as an idea: couldn't it also be that (counterintuitively) one could try raising the VCCPLL to have more room to lower the VCore? The reasoning behind that could be that if the PLL is doing a better job (cleaner clock signals) because of the increased voltage, it's possible for the CPU to run at a lower VCore because of that. – Stefan Seidel – 2013-04-15T14:46:29.870

@Stefan interesting theory - but I'm curious which is scientifically accurate. I guess I could try raising it above the default, and try lowering the try core even more (though it's already pretty low - maybe I'll push the clock up to test) later tonite... Unless David knows one way or the other... – AviD – 2013-04-15T16:27:33.323

3@AviD: Experience seems to show that the PLL generates cleaner clocks with lower voltages in most cases. Cleaner clocks improves overclocking, which should allow a lower core voltage -- in theory. I haven't hear any reports of a higher PLL voltage producing cleaner clock signals. (I guess that's what one might think, but experience has not shown this but in fact the reverse.) – David Schwartz – 2013-04-15T16:49:05.290

@DavidSchwartz Thanks. Can you add your comments into the answer? The real answer to the question is really in the comments... Thanks! – AviD – 2013-04-18T16:33:25.057

As documented here, the VCCPLL should be 1.80V +/- 5% and is specified at a max of 1.5A, which means it draws a maximum power of 2.835W. Since this is such a very low number compared to the >77W (stock, yours is probably higher) that the whole CPU draws, it will not provide significant power usage reductions. Of course you can experiment, but even if you lower it to 1.5V, you have gained a whopping 0.585W advantage, which is probably not worth the instability it may cause. Try sticking to reducing Vcore as much as possible.

Stefan Seidel

Posted 2013-04-15T13:43:22.753

Reputation: 8 812

My i7 930 is more stable with lower CPU PLL, now at 1.7V. – skan – 2015-11-21T11:41:30.493

Thank you, that is very helpful. However I think that linked document is not relevant, as the architectures may have changed substantially - do you know if that is still the case with Ivy Bridge? – AviD – 2013-04-15T14:13:39.887

2Sorry, I have updated the link to the correct Ivy Bridge document and adjusted the numbers accordingly. – Stefan Seidel – 2013-04-15T14:20:39.277