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I understand that the access speed of internal registers is very high compared to that of L1 Cache and L1 Cache can be accessed faster than that of L2 cache which in turn can be accessed faster than that of RAM . But, i wonder why is the size of Internal registers always less than that of L1 Cache and why is the size of L1 cache mostly less that that of L2 cache which in turn is always less than that of RAM size ?