How the speculative load and store happen in modern Intel processor?

Question

I think the store queue is used in modern Intel processors for storing both memory address and store data. They do not go to L1 cache till the commit stage. But I am not 100% sure if it is correct or store is allowed at execution stage i.e., before commit stage. Regarding load, I do not know if there is any load queue, load-store queue or any other structure or the load is allowed to happen from L1 cache at the execution stage i.e., before the commit stage.

I also want to know if there is any Memory dependence predictor in Intel processors that can predict true dependencies between load and store before their addresses are known.

Please help me to clarify my doubts.

Answer 1

The answer is that the load is allowed to happen speculatively but store buffer does not store anything till the retire stage. It is probably because we assume that the outside world is allowed to influence the CPU (CPU can ignore it if found wrong) for load but CPU is not allowed to influence outside world by speculative store (happens only when 100% sure).