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I'm trying to understand how multicore CPU's implement thread synchronisation at the hardware level.
From my research so far I've found that the process involves using a location in memory to act as a lock and for a thread to run its sychronized section of code it needs to aqcuire the lock by using a special instruction to simultaniously read the value of 0 and write a value of 1 to this memory location.
This should work perfectly, however modern CPU's contain multiple levels of per core and shared cache. if a CPU implements cache write-back then the memory location holding the lock value will be out of sync with in L1 cache across cores. If the CPU implements cache write-through protocol then there will be a significant performance hit to every write to memory.
How does the CPU maintain synchronisation of memory locations used as locks in cache?