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Does anyone know what the Arbiter would look like on a DDR memory controller? I was thinking that in order to perform memory access operation reordering for optimisation it may contain a ROB / scheduler / retire like architecture perhaps... Does anyone have an insight into the actual implementation?
Lewis Kelsey
Posted 2018-10-28T15:57:20.577
Reputation: 226
Are you looking for a mechanism to arbitrate memory requests between channels/Ranks...? – lol – 2019-11-13T19:17:55.330