How does a PCI slot work when among PCIe slots?

Question

Lets say a motherboard has 1 PCI slot, is it sharing any bandwidth at all with the PCIe slots? I know PCIe slots have their own dedicated lanes.

Answer 1

PCIe

First, there's actually two types of PCIe lanes on a typical modern (Intel¹) CPU: dedicated lanes from the CPU, and lanes provided by the chipset.

Mainstream consumer CPUs have 16 dedicated lanes, typically used for graphics but also possibly split between two or more slots.

The chipset is also able to provide additional lanes, which communicate with the CPU via DMI (on Intel boards). The number of lanes provided varies, but shares bandwidth with other on-board connectivity, e.g. USB (3.x) and SATA ports.

For example, the H170 chipset provides 16 lanes from the CPU plus up to 16 lanes from the chipset: Intel H170 block diagram²

From 2011-2015, it was common to see 16 PCIe lanes from the CPU plus 8 lanes from the chipset, with the chipset lanes sometimes being lower-bandwidth (PCIe 3.0 vs 2.0).

From 2015 (Skylake) to now, a newer version of DMI and with it the explicit concept of HSIO lanes between CPU and chipset has been introduced, making the max chipset lane count more explicit (with each PCIe lane using one HSIO lane) - but that is rarely reached, since most people would prever to have a decent number of USB, SATA, Ethernet, etc. ports - which use the same HSIO lanes.

So, basically, almost every board should have 16 lanes from the CPU with varying additional lanes provided by the motherboard.

PCI

Where PCIe is point-to-point, with lanes running from CPU to slot (or chipset to slot), PCI is not - rather, it is a shared bus. What this means, practically, is that every PCI slot shares signalling time on the same physical wires, and there is typically only a single PCI bus connected to PCI slots³ in the entire system.

In a modern system, the PCI bus is provided by a PCIe-to-PCI bridge. This is typically independent of any user-visible PCIe lanes - it does not use any of the 16 CPU-provided lanes, though it may take one HSIO lane behind the scenes.

As recently as 2012, the chipset provided direct PCI support without an external bridge, in selected SKUs on up to 7-series (Ivy Bridge) chipsets. The move to dropping support entirely was with 8-series (Haswell) chipsets, though there is still support for the PCI Legacy Mode to on the PCIe root port for legacy PCI address decoding (see Intel 8 Series PCH datasheet, section 5.2.2).

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¹ I believe AMD/Ryzen does something similar, but I'm not as familiar with it.

² Intentionally not embedding the image as the licence is unclear and probably does not allow redistribution under CC-BY-SA.

³ Many internal components are still connected via PCI busses, just not exposed via slots. In fact, one could take each PCIe lane to be a separate PCI bus, as the signalling is compatible. But we're only interested in those busses that are connected to slots.

Answer 2

This answer applies to Intel systems, I'm not sure if things are different on the AMD side.

On older systems the PCI bus connected directly to the ICH/PCH. More modern PCH chips don't have PCI support built-in. So one of the PCIe lanes on the PCH is used to drive a PCIe to PCI bridge chip for the PCI slot(s). Typically all PCI slots will be on the same bus and will share the PCI bus bandwidth.

Also in some cases the same PCI bus that drives the PCI slot(s) may be shared with onboard perhipherals, especially on older systems or systems that have onboard support for legacy interfaces such as firewire.

Finally everything connected via the ICH/PCH (typically this includes among other things onboard SATA, onboard Ethernet, the smaller PCIe slots and any PCI slots) shares a link to the CPU/MCH/IOH. This link has a large but not unlimited bandwidth and can potentially become contended.