The Intel Core 2 Quad 8200 is based on the Intel Core Microarchitecture.
Looking at the performance counter events for that microarchitecture (Chapter 19.10 of Intel Manual 3) you can find an event named L2_LD.(Core, Prefetch, Cache Line State) that reads
This event counts L2 cache read requests coming from the
L1 data cache and L2 prefetchers.
The event can count occurrences:
• For this core or both cores.
• Due to demand requests and L2 hardware prefetch
requests together or separately.
• Of accesses to cache lines at different MESI states.
The L2 cache is the Last Level Cache for Yorkfield-6M (which is the core implementing the Core microarchitecture).
Chapter 35.1 also confirms that the MSR IA32_MISC_ENABLE (1a0h) has bit 9 for disabling the prefetchers.
Thus the prefetchers are there.
The datasheet is meant for electrical engineers, it doesn't describe the functionality of the CPU as it is too complex that it is worth separating it in a second volume.
Benchmarking internal CPU behaviours, like the prefetcher, is tricky. The prefetcher is triggered only by specific patterns.
You are better off with measuring, through performance events, the L2 cache requests due to the prefetcher.
How to accomplish this is beyond the scope of this answer, but you can take a look at the perf tool.
1What're you actually trying to do? – Journeyman Geek – 2016-12-19T07:23:57.063
Measure the effects on cache of particular processes in a real-time Linux system. However the prefetcher may get dirty my measurement. – RicoRico – 2016-12-19T11:28:24.860