Does Intel Q8200 have Cache prefetcher?

0

Intel Processors based on Intel Microarchitecture should support Cache Hardware Prefetching.

I'm using a Q8200 but I cannot find any option in the BIOS to enable/disable the prefetcher. Also I modified the MSR 0x1A0 but it seems to produce no effects on performance (I measured it via a memory benchmark).

Thus, I suspect that Q8200 does not have any cache hardware prefetcher. Also, in the datasheet of Q8000 series cache prefetcher is never mentioned.

Can someone confirm or deny my doubt?

RicoRico

Posted 2016-12-14T17:14:06.167

Reputation: 53

1What're you actually trying to do? – Journeyman Geek – 2016-12-19T07:23:57.063

Measure the effects on cache of particular processes in a real-time Linux system. However the prefetcher may get dirty my measurement. – RicoRico – 2016-12-19T11:28:24.860

Answers

2

The Intel Core 2 Quad 8200 is based on the Intel Core Microarchitecture.

Looking at the performance counter events for that microarchitecture (Chapter 19.10 of Intel Manual 3) you can find an event named L2_LD.(Core, Prefetch, Cache Line State) that reads

This event counts L2 cache read requests coming from the L1 data cache and L2 prefetchers. The event can count occurrences:
• For this core or both cores.
• Due to demand requests and L2 hardware prefetch requests together or separately.
• Of accesses to cache lines at different MESI states.

The L2 cache is the Last Level Cache for Yorkfield-6M (which is the core implementing the Core microarchitecture).

Chapter 35.1 also confirms that the MSR IA32_MISC_ENABLE (1a0h) has bit 9 for disabling the prefetchers.


Thus the prefetchers are there.

The datasheet is meant for electrical engineers, it doesn't describe the functionality of the CPU as it is too complex that it is worth separating it in a second volume.

Benchmarking internal CPU behaviours, like the prefetcher, is tricky. The prefetcher is triggered only by specific patterns.
You are better off with measuring, through performance events, the L2 cache requests due to the prefetcher.

How to accomplish this is beyond the scope of this answer, but you can take a look at the perf tool.

Margaret Bloom

Posted 2016-12-14T17:14:06.167

Reputation: 1 258

The problem is that after disable the prefetchers via 0x1a0, the perf tool seems to continue to log the prefetching events, so I'm not sure if performance counters are not reliable in this case or modifying 0x1a0 does not work. – RicoRico – 2016-12-19T11:31:01.250

1

@RicoRico What events did you use? After a quick tour on the Intel manuals I would use the events -e rD029,rC029 where the first counts the L2 reference due to the PF only and the second counts the L2 ref without the PF (rF029 would count both). I'm not an expert with perf, so check this question about the correct syntax to specify custom events. In this case the event number is 0x29 and the umasks are 0xd0, 0xc0 and 0xf0 respectively.

– Margaret Bloom – 2016-12-19T12:11:00.340

1@RicoRico Amend: The umasks should be 0xdf, 0xcf, 0xff. And so the events should be -e rDF29,rCF29,rFF29 – Margaret Bloom – 2016-12-19T12:18:05.177

Thank you! The default performance counters used by perf are not probably the correct ones. Disabling prefetcher works and rDF29 reports 0! – RicoRico – 2016-12-20T06:24:28.633