How does the CPU know when an interrupt occurs?

Question

I am writing an emulator and can't seem to find info on this. What I know is that devices trigger a pulse on the IRQ wire. But the explanations online don't include how the CPU deals with that. Does an interrupt literally cause the CPU to drop everything and take care of it? Or does the CPU check the state of the IRQ during each cycle? Also, what about other ways of handling interrupts? For example, the Nintendo Game Boy apparently uses a reserved location in memory as an interrupt flag, which tells the CPU where to call a subroutine for handling that interrupt (my best guess is that this flag is written to by DMA). Is this common or standard on older systems?

Answer 1

What I know is that devices trigger a pulse on the IRQ wire.

Maybe a pulse, but more common a level is asserted.
Only after the interrupt is acknowledged is the request line de-asserted.

Does an interrupt literally cause the CPU to drop everything and take care of it?

Effectively yes, in an orderly manner. That's why it's called an "interrupt".

Or does the CPU check the state of the IRQ during each cycle?

No the CPU is literally interrupted (at the completion of an instruction).
But if you look deeper, i.e. how does the CPU itself work, then there is a state machine that examines the IRQ line.

For example, the Nintendo Game Boy apparently uses a reserved location in memory as an interrupt flag, which tells the CPU where to call a subroutine for handling that interrupt

That vaguely sounds like an interrupt vector, which is used in many CPU architectures. But it's not used as an "interrupt flag".

Your questions seem to indicate that you have a weak grasp of that is external to a CPU and what is internal to a CPU. For instance the CPU executes machine instructions fetched from memory. Internal to the CPU there's an instruction decoder. If you describe this internal operation as "the CPU decodes the instruction", then you've created a problem differentiating external versus internal (low-level) operations.