15

4

A minifloat is a binary representation of a floating-point number that has very few bits.

The minifloat in this question will be defined as an 6-bit number `m`

, which has the following representation:

1 bit to repesent the sign of the number. This bit will be

`0`

if the number is positive, and`1`

if the number is negative.3 bits to represent the exponent of the number, offset by

`3`

(i.e. an exponent of`110`

actually represents a factor of 2^{3}, not 2^{6}).- An exponent of
`000`

refers to a subnormal number. The mantissa refers to the fractional part of a number with an integer part of`0`

multiplied by a factor of the lowest possible exponent (in this case, 2^{-2}).

- An exponent of
2 bits to represent the mantissa of the number. If the exponent is anything other than

`000`

or`111`

, the 2 bits represent the fractional part after a`1`

.- An exponent of
`111`

represents`infinity`

if the mantissa is`0`

, and`NaN`

(not a number) otherwise.

- An exponent of

In the Wikipedia article, this would be referred to as a (1.3.2.3) minifloat.

Some examples of this minifloat's representation:

```
000000 = 0.00 = 0
000110 = 1.10 × 2^(1-3) = 0.375
001100 = 1.00 × 2^(3-3) = 1
011001 = 1.01 × 2^(6-3) = 10
011100 = infinity
011101 = NaN
100000 = -0.00 = -0
100011 = -0.11 × 2^(1-3) = -0.1875 (subnormal)
101011 = -1.11 × 2^(2-3) = -0.875
110100 = -1.00 × 2^(5-3) = -4
111100 = -infinity
111111 = NaN
```

Your task is to build a network of two-input NAND gates that takes 6 inputs representing a minifloat `a`

and 6 inputs representing a minifloat `b`

, and returns 6 outputs representing the minifloat `a + b`

.

Your network must properly add subnormals. For example,

`000001`

+`000010`

must equal`000011`

, and`001001`

+`000010`

=`001010`

.Your network must add and subtract infinities properly. Anything finite added to an infinity is the same infinity. Positive infinity plus negative infinity is

`NaN`

.A

`NaN`

plus anything must equal a`NaN`

, although which`NaN`

it equals is up to you.How you handle adding positive zero and negative zero to each other is up to you, although zero plus zero must equal zero.

Your network can implement any of the following rounding rules depending on convenience:

- Round down (toward negative infinity)
- Round up (toward positive infinity)
- Round toward zero
- Round away from zero
- Round to nearest, with halves rounded according to any of the above rules

To simplify things, you may use AND, OR, NOT, and XOR gates in your diagram, with the following corresponding scores:

`NOT: 1`

`AND: 2`

`OR: 3`

`XOR: 4`

Each of these scores corresponds to the number of NAND gates that it takes to construct the corresponding gate.

The logic circuit that uses the fewest NAND gates to correctly implement all the above requirements wins.

2Nice challenge - I'd have to seriously think about this to implement it in code, let alone NAND gates. – Digital Trauma – 2014-04-22T20:26:28.910